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INTEGRATED CIRCUITS
DATA SHEET
TDA9870A Digital TV Sound Processor (DTVSP)
Product specification File under Integrated Circuits, IC02 1998 Aug 10
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
CONTENTS 1 1.1 1.2 1.3 2 2.1 3 4 5 6 6.1 6.2 6.3 7 8 9 10 10.1 10.2 10.3 10.4 10.5 11 12 13 14 15 15.1 15.2 15.3 16 17 18 FEATURES Demodulator and decoder section DSP section Analog audio section GENERAL DESCRIPTION Supported standards ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Description of the demodulator and decoder section Description of the DSP Description of the analog audio section LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS I2C-BUS CONTROL Introduction Power-up state Slave receiver mode Slave transmitter mode Expert mode I2S-BUS DESCRIPTION EXTERNAL COMPONENTS APPLICATION CIRCUITRY PACKAGE OUTLINE SOLDERING Introduction Soldering by dipping or by wave Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
TDA9870A
1998 Aug 10
2
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
1 1.1 FEATURES Demodulator and decoder section
TDA9870A
* Sound IF (SIF) input switch e.g. to select between terrestrial TV SIF and SAT SIF sources * SIF AGC with 24 dB control range * SIF 8-bit Analog-to-Digital Converter (ADC) * Two-carrier multistandard FM demodulation (B/G, D/K and M standard) * Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite sound * Programmable identification (B/G, D/K and M standard) and different identification times. 1.2 DSP section 2 GENERAL DESCRIPTION The TDA9870A is a single-chip Digital TV Sound Processor (DTVSP) for analog multi-channel sound systems in TV sets and satellite receivers. 2.1 Supported standards
* Digital crossbar switch for all digital signal sources and destinations * Control of volume, balance, contour, bass, treble, pseudo stereo, spatial, bass boost and soft-mute * Plop-free volume control * Automatic Volume Level (AVL) control * Adaptive de-emphasis for satellite * Programmable beeper * Monitor selection for FM/AM DC values and signals, with peak detection option * I2S-bus interface for a feature extension (e.g. Dolby surround) with matrix, level adjust and mute. 1.3 Analog audio section
The multistandard/multi-stereo capability of the TDA9870A is mainly of interest in Europe, but also in Hong Kong/Peoples Republic of China and South East Asia. This includes B/G, D/K, I, M and L standard. In other application areas there exists only subsets of those standard combinations otherwise only single standards are transmitted. M standard is transmitted in Europe by the American Forces Network (AFN) with European channel spacing (7 MHz VHF, 8 MHz UHF) and monaural sound. Korea has a stereo sound system similar to Europe and is supported by the TDA9870A. Differences include deviation, modulation contents and identification. It is based on M standard. An overview of the supported standards and sound systems and their key parameters is given in Table 1. The analog multi-channel sound systems (A2, A2+ and A2*) are sometimes also named 2CS (2-Carrier Systems).
* Analog crossbar switch with inputs for mono and stereo (also applicable as SCART 3 input), SCART 1 input/output, SCART 2 input/output and line output * User defined full-level/-3 dB scaling for SCART outputs * Output selection of mono, stereo, dual A/B, dual A or dual B * 20 kHz bandwidth for SCART-to-SCART copies * Standby mode with functionality for SCART copies * Dual audio Digital-to-Analog Converter (DAC) from DSP to analog crossbar switch, bandwidth of 15 kHz * Dual audio ADC from analog inputs to DSP * Two dual audio DACs for loudspeaker (Main) and headphone (Auxiliary) outputs; also applicable for L, R, C and S in the Dolby Pro Logic mode with feature extension.
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
2.1.1 Table 1 ANALOG 2-CARRIER SYSTEMS Frequency modulation SOUND SYSTEM mono A2+ A2 mono A2 A2* CARRIER FREQUENCY (MHz) 4.5 4.5/4.724 5.5/5.742 6.0 6.5/6.742 6.5/6.258 FM DEVIATION (kHz) NOM. 15 15 27 27 27 27 MAX. 25 25 50 50 50 50 OVER 50 50 80 80 80 80
1 1 1 1
TDA9870A
MODULATION SC1 mono
2(L 1
STANDARD M M B/G I D/K D/K Table 2
SC2 -
2(L
BANDWIDTH/ DE-EMPHASIS (kHz/s) 15/75 15/75 (Korea) 15/50 15/50 15/50 15/50
+ R)
- R)
2(L + R)
R - R R
mono
2(L
+ R)
2(L + R)
Identification for A2 systems PARAMETER A2/A2* 54.6875 kHz = 3.5 x line frequency line frequency 117.5 Hz = -------------------------------------133 line frequency 274.1 Hz = -------------------------------------57 50% A2+ (KOREA) 55.0699 kHz = 3.5 x line frequency line frequency 149.9 Hz = -------------------------------------105 line frequency 276.0 Hz = -------------------------------------57 50%
Pilot frequency Stereo identification frequency Dual identification frequency AM modulation depth
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
2.1.2 SATELLITE SYSTEMS
TDA9870A
An important specification for satellite TV reception is the "Astra specification". The TDA9870A is suited for the reception of Astra and other satellite signals. Table 3 FM satellite sound CARRIER FREQUENCY (MHz) 6.50(1) 7.02/7.20 7.38/7.56 7.74/7.92 8.10/8.28 MODULATION INDEX 0.26 0.15 0.15 0.15 0.15 MAXIMUM FM DEVIATION (kHz) 85 50 50 50 50 MODULATION mono m/st/d(2) m/st/d(2) m/st/d(2) m/st/d(2) BANDWIDTH/ DE-EMPHASIS (kHz/s) 15/50(1) 15/adaptive(3) 15/adaptive(3) 15/adaptive(3) 15/adaptive(3)
CARRIER TYPE Main Sub Sub Sub Sub Notes
1. For other satellite systems, frequencies of, for example, 5.80, 6.60 or 6.65 MHz can also be received. A de-emphasis of 60 s, or in accordance with J17, is available. 2. m/st/d = mono or stereo or dual language sound. 3. Adaptive de-emphasis is compatible to transmitter specification. 3 ORDERING INFORMATION TYPE NUMBER TDA9870A PACKAGE NAME SDIP64 DESCRIPTION plastic shrink dual in-line package; 64 leads (750 mil) VERSION SOT274-1
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
4 BLOCK DIAGRAM
TDA9870A
handbook, full pagewidth
SIF2 10 P1 P2 ADDR1 ADDR2 SCL SDA 9 20 3 13 4 5 I2C-BUS INTERFACE INPUT SWITCH AGC, ADC
SIF1 12
7 SUPPLY SOUND IF (SIF) 6 11 8
VDEC1 VSSA1 Vref1 Iref
IDENTIFICATION
FM (AM) DEMODULATION
33 XTALI XTALO SYSCLK 18 19 21 CLOCK A2/SATELLITE DECODER 34 36 37 31 32 ANALOG CROSSBAR SWITCH 29 47 48 PEAK DETECTION LEVEL ADJUST 51 52 63 62
SCIR1 SCIL1 SCIR2 SCIL2 EXTIR EXTIL MONOIN SCOR1 SCOL1 SCOR2 SCOL2 LOR LOL
SDI1 SDI2 SDO1 SDO2 SCK WS
27 26 25 24 22 23 I2S-BUS INTERFACE DIGITAL SELECT ADC (2) 1 2 41 42 44 45 i.c. i.c. i.c. i.c. i.c. i.c.
VDDD1 VDDD2 VSSD1 VSSD2 VSSD3 VSSD4 CRESET
15 64 14 49 35 17 16 AUDIO PROCESSING DIGITAL SUPPLY 59 38 39 VDDA2 VDEC2 Vref(p) Vref(n) Vref2 Vref3 VSSA2 VSSA3 VSSA4 DAC (2) 54 55 PCAPR PCAPL
TDA9870A
DAC (2) TEST1 TEST2 28 30 TEST DAC (2)
40 SUPPLY SCART, DAC, ADC 46 53 43 56 50
61
60
58
57
MHB110
MOL
MOR
AUXOL
AUXOR
Fig.1 Block diagram.
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
5 PINNING SYMBOL i.c. i.c. ADDR1 SCL SDA VSSA1 VDEC1 Iref P1 SIF2 Vref1 SIF1 ADDR2 VSSD1 VDDD1 CRESET VSSD4 XTALI XTALO P2 SYSCLK SCK WS SDO2 SDO1 SDI2 SDI1 TEST1 MONOIN TEST2 EXTIR EXTIL SCIR1 SCIL1 VSSD3 SCIR2 SCIL2 VDEC2 Vref(p) 1998 Aug 10 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 I/O - - I I I/O supply - - I/O I - I I supply supply - supply I O I/O O I/O I/O O O I I I I I I I I I supply I I - - internally connected; note 1 internally connected; note 1 first I2C-bus slave address modifier I2C-bus clock input I2C-bus data input/output supply ground 1; analog front-end circuitry DESCRIPTION
TDA9870A
positive power supply voltage 1 decoupling; analog front-end circuitry resistor for reference current generator; analog front-end circuitry first general purpose I/O pin sound IF input 2 reference voltage; analog front-end circuitry sound IF input 1 second I2C-bus slave address modifier supply ground 1; digital circuitry digital supply voltage 1; digital circuitry capacitor for power-on reset supply ground 4; digital circuitry crystal oscillator input crystal oscillator output second general purpose I/O pin system clock output I2S-bus clock input/output I2S-bus word select input/output I2S-bus data output 2 I2S-bus data output 1 I2S-bus data input 2 I2S-bus data input 1 first test pin; connected to VSSD1 for normal operation audio mono input second test pin; connected to VSSD1 for normal operation external audio input right channel external audio input left channel SCART 1 input right channel SCART 1 input left channel supply ground 3; digital circuitry SCART 2 input right channel SCART 2 input left channel positive power supply voltage 2 decoupling; audio analog-to-digital converter circuitry positive reference voltage; audio analog-to-digital converter circuitry 7
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
SYMBOL Vref(n) i.c. i.c. VSSA2 i.c. i.c. Vref2 SCOR1 SCOL1 VSSD2 VSSA4 SCOR2 SCOL2 Vref3 PCAPR PCAPL VSSA3 AUXOR AUXOL VDDA MOR MOL LOL LOR VDDD2 Notes
PIN 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
I/O - - - supply - - - O O supply supply O O - - - supply O O supply O O O O supply internally connected; note 2 internally connected; note 3
DESCRIPTION reference voltage ground; audio analog-to-digital converter circuitry
supply ground 2; audio analog-to-digital converter circuitry internally connected; note 3 internally connected; note 2 reference voltage; audio analog-to-digital converter circuitry SCART 1 right channel output SCART 1 left channel output supply ground 2; digital circuitry supply ground 4; audio operational amplifier circuitry SCART 2 right channel output SCART 2 left channel output reference voltage; audio digital-to-analog converter and operational amplifier circuitry post-filter capacitor pin right channel, audio digital-to-analog converter post-filter capacitor pin left channel, audio digital-to-analog converter supply ground 3; audio digital-to-analog converter circuitry headphone (Auxiliary) right channel output headphone (Auxiliary) left channel output positive analog power supply voltage; analog circuitry loudspeaker (Main) right channel output loudspeaker (Main) left channel output line output left channel line output right channel digital supply voltage 2; digital circuitry
1. Test pin, CMOS 3-state stage, pull-up resistor, can be connected to VSS. 2. Test pin, CMOS level input, pull-up resistor, can be connected to VSS. 3. Test pin, CMOS 3-state stage, can be connected to VSS.
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
handbook, halfpage
i.c. 1 i.c. 2 ADDR1 3 SCL 4 SDA 5 VSSA1 6 VDEC1 7 Iref 8 P1 9 SIF2 10 Vref1 11 SIF1 12 ADDR2 13 VSSD1 14 VDDD1 15 CRESET 16 VSSD4 17 XTALI 18 XTALO 19 P2 20 SYSCLK 21 SCK 22 WS 23 SDO2 24 SDO1 25 SDI2 26 SDI1 27 TEST1 28 MONOIN 29 TEST2 30 EXTIR 31 EXTIL 32
MHB111
64 VDDD2 63 LOR 62 LOL 61 MOL 60 MOR 59 VDDA 58 AUXOL 57 AUXOR 56 VSSA3 55 PCAPL 54 PCAPR 53 Vref3 52 SCOL2 51 SCOR2 50 VSSA4 49 VSSD2
TDA9870A
48 SCOL1 47 SCOR1 46 Vref2 45 i.c. 44 i.c. 43 VSSA2 42 i.c. 41 i.c. 40 Vref(n) 39 Vref(p) 38 VDEC2 37 SCIL2 36 SCIR2 35 VSSD3 34 SCIL1 33 SCIR1
Fig.2 Pin configuration.
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
6 6.1 6.1.1 FUNCTIONAL DESCRIPTION Description of the demodulator and decoder section SIF INPUT 6.1.5 FM IDENTIFICATION
TDA9870A
Two input pins are provided, SIF1 e.g. for terrestrial TV and SIF2 e.g. for a satellite tuner. For higher SIF signal levels the SIF input can be attenuated with an internally switchable -10 dB resistor divider. As no specific filters are integrated, both inputs have the same specification giving flexibility in application. The selected signal is passed through an AGC circuit and then digitized by an 8-bit ADC operating at 24.576 MHz. 6.1.2 AGC
The identification of the FM sound mode is performed by AM synchronous demodulation of the pilot signal and narrow-band detection of the identification frequencies. The result is available via the I2C-bus interface. A selection can be made via the I2C-bus for B/G, D/K and M standard and for three different modes that represent different trade-offs between speed and reliability of identification. 6.1.6 CRYSTAL OSCILLATOR
The crystal oscillator (XO) is illustrated in Fig.8 (see Chapter 12). The circuitry of the XO is fully integrated, only the external 24.576 MHz crystal is needed. 6.1.7 TEST PINS
The gain of the AGC amplifier is controlled from the ADC output by means of a digital control loop employing hysteresis. The AGC has a fast attack behaviour to prevent ADC overloads and a slow decay behaviour to prevent AGC oscillations. For AM demodulation the AGC must be switched off. When switched off, the control loop is reset and fixed gain settings can be chosen (see Table 14; subaddress 0). The AGC can be controlled via the I2C-bus. Details can be found in the I2C-bus register definitions (see Chapter 10). 6.1.3 MIXER
Both test pins are active HIGH, in normal operation of the device they are connected to VSSD1. Test functions are for manufacturing tests only and are not available to customers. Without external circuitry these pads are pulled down to LOW level with internal resistors. 6.1.8 POWER FAIL DETECTOR
The digitized input signal is fed to the mixers, which mix one or both input sound carriers down to zero IF. A 24-bit control word for each carrier sets the required frequency. Access to the mixer control word registers is via the I2C-bus. 6.1.4 FM AND AM DEMODULATION
The power fail detector monitors the internal power supply for the digital part of the device. If the supply has temporarily been lower than the specified lower limit, the power-on reset bit POR, transmitter register subaddress 0 (see Section 10.4.1), will be set to HIGH. The CLRPOR bit, slave register subaddress 1 (see Section 10.3.2), resets the power-on reset flip-flop to LOW. If this is detected, an initialization of the TDA9870A has to be performed to ensure reliable operation.
An FM or AM input signal is fed via a band-limiting filter to a demodulator that can be used for either FM or AM demodulation. Apart from the standard (fixed) de-emphasis characteristic, an adaptive de-emphasis is available for encoded satellite programs. A stereo decoder recovers the left and right signal channels from the demodulated sound carriers. Both the European and Korean stereo systems are supported.
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1998 Aug 10
2 2 2 LEVEL ADJUST from ADC 2 DC FILTER 2 4 LEVEL ADJUST I2S1 2 6 2 LEVEL ADJUST I2S2 2 8
6.2 Description of the DSP
Philips Semiconductors
Digital TV Sound Processor (DTVSP)
2
MATRIX
AUTOMATIC VOLUME LEVEL VOLUME SOFT-MUTE BASS/TREBLE BEEPER
SPATIAL PSEUDO VOLUME BASS/TREBLE BASS BOOST CONTOUR SOFT-MUTE BEEPER
2
LS
2 DIGITAL CROSSBAR SELECT 2
MATRIX
2
HP
LEVEL ADJUST AND MUTE MATRIX
2
I2S1
11
2 MATRIX FM 2 DC FILTER ADAPTIVE DE-EMPHASIS FIXED DE-EMPHASIS LEVEL ADJUST MATRIX 2 MATRIX 10 2 4 14
LEVEL ADJUST AND MUTE
2
I2S2
LEVEL ADJUST
2
DAC
MONITOR SELECT PEAK DETECTION
1
I2C-bus
MHB112
Product specification
TDA9870A
Fig.3 DSP data flow diagram.
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
6.2.1 LEVEL SCALING
TDA9870A
Pseudo stereo is based on a phase shift in one channel via a 2nd-order all-pass filter. There are fixed coefficient sets to provide 90 degrees phase shift at frequencies of 150, 200 and 300 Hz. Volume is controlled individually for each channel ranging from +24 to -83 dB with 1 dB resolution. There is also a mute position. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for volume control is identical to the volume setting in dBs (e.g. the I2C-bus data byte +10 sets the new volume value to +10 dB). Balance can be realized by independent control of the left and right channel volume settings. Contour is adjustable between 0 and +18 dB with 1 dB resolution. This function is linked to the volume setting by means of microcontroller software. Bass is adjustable between +15 and -12 dB with 1 dB resolution and treble is adjustable between 12 dB with 1 dB resolution. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for contour, bass or treble is identical to the new contour, bass or treble setting in dBs (e.g. the I2C-bus data byte +8 sets the new value to +8 dB). Extra bass boost is provided up to 20 dB with 2 dB resolution. The implemented coefficient set serves merely as an example on how to use this filter. The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The frequency can be selected via the I2C-bus. The beeper output signal is added to the loudspeaker and headphone channel signals. The beeper volume is adjustable with respect to full scale between 0 and -93 dB with 3 dB resolution. The beeper is not effected by mute. Soft mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft mute is completed. A smooth fading is achieved by a cosine masking. 6.2.5 HEADPHONE (AUXILIARY) CHANNEL
All input channels to the digital crossbar switch (except for the loudspeaker feedback path) are equipped with a level adjust facility to change the signal level in a range of 15 dB. It is recommended to scale all input channels to be 15 dB below full scale (-15 dB full scale) under nominal conditions. 6.2.2 FM (AM) PATH
A high-pass filter suppresses DC offsets from the FM demodulator, due to carrier frequency offsets, and supplies the monitor/peak function with DC values and an unfiltered signal, e.g. for the purpose of carrier detection. The de-emphasis function offers fixed settings for the supported standards (50 s, 60 s and 75 s). An adaptive de-emphasis is available for Wegener-Panda 1 encoded programs. A matrix performs the dematrixing of the A2 stereo, dual and mono signals. 6.2.3 MONITOR
This function provides data words from a number of locations of the signal processing paths to the I2C-bus interface (2 data bytes). Signal sources include the FM demodulator outputs, most inputs to the digital crossbar switch and the outputs of the ADC. Source selection and data read-out is performed via the I2C-bus. Optionally, the peak value can be measured instead of simply taking samples. The internally stored peak value is reset to zero when the data is read via the I2C-bus. The monitor function may be used, for example, for signal level measurements or carrier detection. 6.2.4 LOUDSPEAKER (MAIN) CHANNEL
The matrix provides the following functions; forced mono, stereo, channel swap, channel 1, channel 2 and spatial effects. There are fixed coefficient sets for spatial settings of 30%, 40% and 52%. The Automatic Volume Level (AVL) function provides a constant output level of -23 dB full scale for input levels between 0 and -29 dB full scale. There are some fixed decay time constants to choose from, i.e. 2, 4 and 8 s.
The matrix provides the following functions; forced mono, stereo, channel swap, channel 1 and channel 2 (or C and S in Dolby Surround Pro Logic mode). Volume is controlled individually for each channel in a range from +24 to -83 dB with 1 dB resolution. There is also a mute position.
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for volume control is identical to the volume setting in dB (e.g. the I2C-bus data byte +10 sets the new volume value to +10 dB). Balance can be realized by independent control of the left and right channel volume settings. Bass is adjustable between +15 and -12 dB with 1 dB resolution and treble is adjustable between 12 dB with 1 dB resolution. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for bass or treble is identical to the new bass or treble setting in dB (e.g. the I2C-bus data byte +8 sets the new value to +8 dB). The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The frequency can be selected via the I2C-bus. The beeper output signal is added to the loudspeaker and headphone channel signals. The beeper volume is adjustable with respect to full scale between 0 and -93 dB with 3 dB resolution. The beeper is not effected by mute. Soft mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft mute is completed. A smooth fading is achieved by a cosine masking. 6.2.6 FEATURE INTERFACE 6.2.7
TDA9870A
CHANNEL FROM THE AUDIO ADC
The signal level at the output of the ADC can be adjusted in a range of 15 dB with 1 dB resolution. The audio ADC itself is scaled to a gain of -6 dB. 6.2.8 CHANNEL TO THE ANALOG CROSSBAR PATH
Level adjust with control positions 0 dB, +3 dB, +6 dB and +9 dB. 6.2.9 DIGITAL CROSSBAR SWITCH (see Fig.6)
Input channels to the crossbar switch are from the audio ADC, I2S1, I2S2, FM path and from the loudspeaker channel path after matrix and AVL. Output channels comprise loudspeaker, headphone, I2S1, I2S2 and the audio DACs for line output and SCART. The I2S1 and I2S2 outputs also provide digital outputs from the loudspeaker and headphone channels, but without the beeper signals. 6.2.10 GENERAL
The feature interface comprises two I2S-bus input/output ports and a system clock output. Each I2S-bus port is equipped with level adjust facilities that can change the signal level in a range of 15 dB with 1 dB resolution. Outputs can be disabled to improve EMC performance. The I2S-bus output matrix provides the following functions; forced mono, stereo, channel swap, channel 1 and channel 2. One example of how the feature interface can be used in a TV set is to connect an external Dolby Surround Pro Logic DSP, such as the SAA7710, to the I2S-bus ports. Outputs must be enabled and a suitable master clock signal for the DSP can be taken from pin SYSCLK. A stereo signal from any source will be output on one of the I2S-bus serial data outputs and the four processed signal channels will be entered at both I2S-bus serial data inputs. Left and right could then be output to the power amplifiers via the Main channel, centre and surround via the Auxiliary channel.
There are a number of functions that can provide signal gain, e.g. volume, bass and treble control. Great care has to be taken when using gain with large input signals in order not to exceed the maximum possible signal swing, which would cause severe signal distortion. The nominal signal level of the various signal sources to the digital crossbar switch should be 15 dB below digital full scale (-15 dB full scale). This means that a volume setting of, say, +15 dB would just produce a full scale output signal and not cause clipping, if the signal level is nominal. Sending illegal data patterns via the I2C-bus will not cause any changes of the current setting for the volume, bass, treble, bass boost and level adjust functions. 6.2.11 EXPERT MODE
The TDA9870A provides a special expert mode that gives direct write access to the internal Coefficient RAM (CRAM) of the DSP. It can be used to create user-defined characteristics, such as a tone control with different corner frequencies or special boost/cut characteristics to correct the low-frequency loudspeaker and/or cabinet frequency responses by means of the bass boost filter. However, this mode must be used with great care. More information on the functions of this device, such as the number of coefficients per function, their default values, memory addresses, etc., can be made available on request.
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
6.2.12 Table 4 OVERVIEW OF DSP FUNCTIONS Overview of DSP functions FUNCTION Bass control for loudspeaker and headphone output EXPERT MODE yes resolution resolution at frequency Treble control for loudspeaker and headphone output control range yes resolution resolution at frequency Contour for loudspeaker output yes Bass boost for loudspeaker output yes control range resolution resolution at frequency control range resolution resolution at frequency corner frequency Volume control for each separate channel in loudspeaker and headphone output Soft-mute for loudspeaker and headphone output Spatial effects Pseudo stereo Beeper additional to the signal in the loudspeaker and headphone channel control range no resolution mute position at step no yes yes processing time anti-phase crosstalk positions 90 degree phase shift at frequency beep frequencies yes control range resolution mute position at step Automatic Volume Level (AVL) yes step width AVL output level for an input level between 0 and -29 dB full scale attack time decay time constant General Level adjust Level adjust outputs I2S1 I2S1 and and I2S2 I2S2 yes no inputs no yes -1 dB bandwidth of DSP control range resolution control range resolution mute position at step Level adjust analog crossbar path control positions PARAMETER control range
TDA9870A
VALUE -12 to +15 1 40 -12 to +12 1 14 0 to +18 1 40 0 to +20 2 20 350 -83 to +24 1 10101100 32 30, 40 and 52 150, 200 and 300 see Section 10.3.38 0 to -93 3 00100000 quasi continuously -23 10 2, 4 and 8 14.5 -15 to +15 1 -15 to +15 1 00010000 0, 3, 6 and 9
UNIT dB dB Hz dB dB kHz dB dB Hz dB dB Hz Hz dB dB ms % Hz dB dB
dBFS ms s Hz kHz dB dB dB dB dB
-3 dB lower corner frequency of DSP 10
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
FUNCTION Level adjust audio ADC outputs Level adjust FM path
EXPERT MODE yes yes resolution
PARAMETER control range control range resolution
VALUE +15 to -15 1 +15 to -15 1
UNIT dB dB dB dB
6.3
Description of the analog audio section
handbook, full pagewidth
SCART 1
2
-3 dB
2
2
ANALOG MATRIX
2
3 dB 0 dB
2
SCART 1
2 SCART 2 2 -3 dB 2 ANALOG CROSSBAR SWITCH
ANALOG MATRIX
2
3 dB 0 dB
2
SCART 2
external mono
2
2
ANALOG MATRIX
2
3 dB 0 dB
2
Line output
2
D A
2
2
A D
2
FM I2S1 I2S2 I2S1 I2S2
2 2 2 2 2
DSP AND DIGITAL CROSSBAR SWITCH
2
D A
2
Main
2
D A
2
Auxiliary
MHB113
Fig.4 Block diagram for the audio section.
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
6.3.1 ANALOG CROSSBAR SWITCH AND ANALOG MATRIX (see also Fig.6) 6.3.2 SCART INPUTS
TDA9870A
There are a number of analog input and output ports with the TDA9870A. Analog source selector switches are employed to provide the desired analog signal routing capability. The analog signal routing is performed by the analog crossbar switch section. A dual audio ADC provides the connection to the DSP section and a dual audio DAC provides the connection from the DSP section to the analog crossbar switch. The digital signal routing is performed by a digital crossbar switch. The basic signal routing philosophy of the TDA9870A is that each switch handles two signal channels at the same time, e.g. left and right, language A and B, directly at the source. Each source selector switch is followed by an analog matrix to perform further selection tasks, such as putting a signal from one input channel, say language A, to both output channels or for swapping left and right channels. The analog matrix provides the functions given in Table 5 (see also Fig.5). Table 5 Analog matrix functions MATRIX OUTPUT MODE LEFT OUTPUT 1 2 3 4 left input right input left input right input RIGHT OUTPUT right input left input left input right input
The SCART specification allows for a signal level of up to 2 V (RMS). Because of signal handling limitations, due to the 5 V supply voltage of the TDA9870A, it is necessary to have fixed 3 dB attenuators at the SCART inputs to obtain a 2 V input. This results in a -3 dB SCART-to-SCART copy gain. If 0 dB copy gain is preferred (with maximum 1.4 V input), there are 3 dB and 0 dB amplifiers at the outputs of SCART 1 and SCART 2 and at the line output. The input attenuator is realized by an external series resistor in combination with the input impedance, both of which form a voltage divider. With this voltage divider the maximum SCART signal level of 2 V (RMS) is scaled down to 1.4 V (RMS) at the input pin. 6.3.3 EXTERNAL AND MONO INPUTS
The 3 dB input attenuators are not required for the external and mono inputs, because those signal levels are under control of the TV designer. The maximum allowed input level is 1.4 V (RMS). By adding external series resistors, the external inputs can be used as an additional SCART input. 6.3.4 SCART OUTPUTS
The SCART outputs employ amplifiers with two gain settings. The gain can be set to 3 dB or to 0 dB via the I2C-bus. The 3 dB position is needed to compensate for the 3 dB attenuation at the SCART inputs should SCART-to-SCART copies with 0 dB gain be preferred [under the condition of 1.4 V (RMS) maximum input level]. The 0 dB position is needed, for example, for an external-to-SCART copy with 0 dB gain.
handbook, halfpage
left input
right input
ANALOG MATRIX
left output right output
MGK110
Fig.5 Analog matrix.
All switches and matrices are controlled via the I2C-bus.
1998 Aug 10
16
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
6.3.5 LINE OUTPUT 6.3.8 DUAL AUDIO ADC
TDA9870A
The line output can provide an unprocessed copy of the audio signal in the loudspeaker channels. This can be either an external signal that comes from the dual audio ADC, or a signal from an internal digital audio source that comes from the dual audio DAC. The line output employs amplifiers with two gain settings. The 3 dB position is needed to compensate for the attenuation at the SCART inputs, while the 0 dB position is needed, for example, for non-attenuated external or internal digital signals (see Section 6.3.4). 6.3.6 LOUDSPEAKER (MAIN) AND HEADPHONE (AUXILIARY)
OUTPUTS
There is one dual audio ADC in the TDA9870A for the connection of the analog crossbar switch section to the DSP. The dual audio ADC consists of two bitstream 3rd-order sigma-delta audio ADCs and a high-order decimation filter. 6.3.9 STANDBY MODE
The standby mode (subaddress 1, bit 5) disables most functions and reduces power dissipation. The analog crossbar switch and the SCART section remains operational and can be controlled by the I2C-bus to support copying of analog signals from SCART-to-SCART. Unused internal registers may lose their information in standby mode. Therefore, the device needs to be initialized on returning to normal operation. This can be accomplished in the same way as after a power-on reset. 6.3.10 SUPPLY GROUND
Signals from any audio source can be applied to the loudspeaker and to the headphone output channels via the digital crossbar switch and the DSP. 6.3.7 DUAL AUDIO DAC
The TDA9870A contains three dual audio DACs, one for the connection from the DSP to the analog crossbar switch section and two for the loudspeaker and headphone outputs. Each of the three dual low-noise high-dynamic range DACs consists of two 15-bit DACs with current outputs, followed by a buffer operational amplifier. The audio DACs operate with four-fold oversampling and noise shaping.
The different supply grounds VSSX are internally connected via substrate. It is therefore recommended to connect all ground pins externally close to the pins by a copper plane.
1998 Aug 10
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1998 Aug 10
SCART 1 SCART 2 ADC -6 dB external ADC LEVEL ADJUST mono FM/AM part FM/AM DEMODULATOR ADAPTIVE DE-EMPHASIS FIXED DE-EMPHASIS STEREO DECODER FM LEVEL ADJUST
Philips Semiconductors
Digital TV Sound Processor (DTVSP)
DIGITAL MATRIX
AUTOMATIC VOLUME LEVEL
LOUDSPEAKER CHANNEL PROCESSING
Main DAC
DIGITAL MATRIX
HEADPHONE CHANNEL PROCESSING
Auxiliary DAC
DIGITAL MATRIX
I2S1 OUTPUT LEVEL ADJUST
I2S1 I2S2
18
DIGITAL MATRIX I2S2 OUTPUT LEVEL ADJUST ANALOG MATRIX BUFFER 0/+3 dB Line I2S1 I2S1 INPUT LEVEL ADJUST ANALOG MATRIX DAC GAIN BUFFER 0/+3 dB SCART 1 DIGITAL MATRIX DAC SCART 2 I2S2 I2S2 INPUT LEVEL ADJUST ANALOG MATRIX BUFFER 0/+3 dB
MHB114
Product specification
TDA9870A
Fig.6 Audio signal flow diagram.
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
7 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VDD II/O(max) IDDD, ISSD Ilu(prot) Ptot Tstg Tamb Ves PARAMETER DC supply voltage voltage differences between two VDD pins maximum input/output voltage DC VDD or VSS current per digital supply pin latch-up protection current total power dissipation storage temperature operating ambient temperature electrostatic handling note 1 note 2 Notes 1. Human body model: C = 100 pF; R = 1.5 k. 2. Machine model: C = 200 pF; L = 0.75 H; R = 0 . 8 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 40 CONDITIONS - -0.5 - 100 - -55 -20 2000 200 MIN. -0.5
TDA9870A
MAX. +6.0 550 180 - 1.2 +125 +70 - -
UNIT V mV mA mA W C C V V
VDD + 0.5 V
UNIT K/W
1998 Aug 10
19
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
9 CHARACTERISTICS VSIF(p-p) = 300 mV; AGCOFF = 0; AGCSLOW = 0; AGCLEV = 0; level and gain setting in accordance with note 3; VDD = 5 V; Tamb = 25 C; settings in accordance with B/G standard; FM deviation 50 kHz; fmod = 1 kHz; FM sound parameters in accordance with system A2; 1 k measurement source resistance for AF inputs; unless otherwise specified; with external components of Fig.8. SYMBOL Supplies VDDD1 VSSD1 IDDD1 VDDD2 VSSD2 IDDD2 VSSD3 VSSD4 VDDA IDDA VSSA1 VSSA2 VSSA3 VSSA4 VDEC1 Vref1 Iref1(sink) VDEC2 Vref2 ZVref2-VDEC2 ZVref2-VSSA2 Vref3 ZVref3-VDDA ZVref3-VSSA3 digital supply voltage 1 digital supply ground 1 digital supply current 1 digital supply voltage 2 digital supply ground 2 digital supply current 2 digital supply ground 3 digital supply ground 4 analog supply voltage analog supply current for DAC part analog ground for analog front-end analog ground for audio ADC part analog ground for audio DAC part analog ground for SCART note 1 VDDD2 = 5.0 V; SYSCLOCK off note 1 note 1 note 1 VDDD1 = 5.0 V 4.75 - 53 4.75 - 0.1 - - 4.75 VDDA = 5.0 V; digital silence 44 note 1 note 1 note 1 - - - - 5.0 0.0 68 5.0 0.0 0.4 0.0 0.0 5.0 56 0.0 0.0 0.0 0.0 5.5 - 83 5.5 - 2 - - 5.5 68 - - - - V V mA V V mA V V V mA V V V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Demodulator supply decoupling and references analog supply decoupling voltage for demodulator part analog reference voltage for demodulator part Vref1 sink current analog supply decoupling voltage for audio ADC part reference voltage for audio ADCs impedance Vref2 to VDEC2 impedance Vref2 to VSSA2 reference voltage for audio DAC and operational amplifier impedance Vref3 to VDDA impedance Vref3 to VSSA3 referenced to VDDA/VSSA3 referenced to VDEC2/VSSA2 3.0 - - 3.3 2 200 3.6 - - V V A
Audio supply decoupling and references 3.0 - - - - - - 3.3 50 20 20 50 20 20 3.6 - - - - - - V % k k % k k
1998 Aug 10
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
SYMBOL Power fail detector Vth(pf)
PARAMETER
CONDITIONS -
MIN.
TYP. -
MAX.
UNIT
power fail threshold level
3.9
V
Digital inputs and outputs INPUTS
CMOS level input, pull-down (pins TEST1 and TEST2)
VIL VIH Ci Zi VIL VIH Vhys Ci Zi LOW-level input voltage HIGH-level input voltage input capacitance input impedance - - - - - - - - - 50 - 1.3 - 50 0.3VDDD V - 10 - V pF k 0.7VDDD -
CMOS level input, hysteresis, pull-up (pin CRESET)
LOW-level input voltage HIGH-level input voltage hysteresis voltage input capacitance input impedance 0.3VDDD V - - 10 - V V pF k 0.7VDDD -
INPUTS/OUTPUTS
I2C-bus level input with Schmitt trigger, open-drain output stage, 400 kHz I2C operation and level (pins SCL and SDA)
VIL VIH Vhys ILI Ci VOL CL LOW-level input voltage HIGH-level input voltage hysteresis voltage input leakage current input capacitance LOW-level output voltage load capacitance - - - - - - - 0.05VDDD - - - - 0.3VDDD V - - 10 10 0.6 400 V V A pF V pF 0.7VDDD -
TTL/CMOS level, 4 mA 3-state output stage, pull-up (pins ADDR1, ADDR2, P1, P2, SCK, WS, SDO1, SDO2, SDI1 and SDI2)
VIL VIH Ci VOL VOH CL Zi LOW-level input voltage HIGH-level input voltage input capacitance LOW-level output voltage HIGH-level output voltage load capacitance input impedance - 2.0 - - 2.4 - - - - - - - - 50 0.8 - 10 0.4 - 100 - V V pF V V pF k
1998 Aug 10
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
SYMBOL OUTPUTS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CMOS level output, 4 mA 3-state output stage, slew rate controlled (pin SYSCLK)
VOL VOH CL ILIZ VSIF(max)(p-p) LOW-level output voltage HIGH-level output voltage load capacitance 3-state leakage current Vi = 0 to VDDD SIF input level adjust 0 dB SIF input level adjust -10 dB SIF input level adjust 0 dB SIF input level adjust -10 dB - - - - - - - - 4 AGCLEV = 0 B/G standard; THD < 1% terrestrial FM; level adjust 0 dB NFM bandwidth = 6 MHz; white noise for S/N = 40 dB; "CCIR468"; quasi peak fi = 4 to 9.2 MHz; note 2 10 - 100 150 - - - - 0.3VDDD V - 100 10 - - - - - 9.2 - 11 - - - V pF A 0.7VDDD -
SIF1 and SIF2 analog inputs maximum composite SIF input voltage for clipping (peak-to-peak value) minimum composite SIF input voltage for lower limit of AGC (peak-to-peak value) AGC range input frequency input resistance input capacitance FM deviation FM deviation full-scale level FM carrier C/Nc ratio 941 2976 59 188 24 - - 7.5 - - 77 mV mV mV mV dB MHz k pF kHz kHz dB FM ------------Hz
VSIF(min)(p-p)
AGC fi Ri Ci fFM fFM(FS) C/NFM
ct
crosstalk attenuation SIF1 to SIF2
50
-
-
dB
Demodulator performance; note 3 THD + N total harmonic distortion plus noise signal-to-noise ratio from FM source to any output; Vo = 1 V (rms) with low-pass filter - 0.3 0.5 %
S/N
SC1 from FM source to any 64 output; Vo = 1 V (rms); "CCIR468"; quasi peak SC2 from FM source to any 60 output; Vo = 1 V (rms); "CCIR468"; quasi peak
70
-
dB
66
-
dB
B-3dB fres
-3 dB bandwidth frequency response 20 Hz to 14 kHz
from FM source to any output from FM to any output; fref = 1 kHz; inclusive pre-emphasis and de-emphasis note 4 22
14.5 -
15 2
- -
kHz dB
cs(dual) 1998 Aug 10
dual signal channel separation
65
70
-
dB
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
SYMBOL cs(stereo) AM
PARAMETER stereo channel separation AM suppression for FM note 5
CONDITIONS AM: 1 kHz, 30% modulation; reference: 1 kHz, 50 kHz deviation SIF level 100 mV (RMS); 54% AM; 1 kHz AF; "CCIR468"; quasi peak
MIN. 40 50 45 -
TYP. - -
MAX.
UNIT dB dB
S/NAM
AM demodulation
36
45
-
dB
IDENTIFICATION FOR FM SYSTEMS modp C/Np fident pilot modulation for identification pilot sideband C/N for identification start identification window B/G stereo slow mode medium mode fast mode B/G dual slow mode medium mode fast mode tident(on) total identification time ON slow mode medium mode fast mode tident(off) total identification time OFF slow mode medium mode fast mode Analog audio inputs MONO INPUT AND EXTERNAL INPUT Vi(nom)(rms) Vi(clip)(rms) Ri SCART INPUTS Vi(nom)(rms) nominal level input voltage at input pin (RMS value) clipping level input voltage at input pin (RMS value) input resistance -3 dB divider with external 15 k resistor; notes 3 and 7 -3 dB divider with external 15 k resistor; THD < 3%; notes 6 and 7 note 6 - 350 - mV nominal level input voltage (RMS value) clipping level input voltage (RMS value) input resistance note 3 THD < 3%; note 6 note 6 - 1250 28 500 1400 35 - - 42 mV mV k 273.44 272.07 270.73 - - - - - - - - - - - - - - - 274.81 276.20 277.60 2 1 0.5 2 1 0.5 Hz Hz Hz s s s s s s 116.85 116.11 114.65 - - - 118.12 118.89 120.46 Hz Hz Hz 25 - 50 27 75 - % dB -----Hz
Vi(clip)(rms)
1250
1400
-
mV
Ri
28
35
42
k
1998 Aug 10
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
SYMBOL Analog audio outputs
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
LOUDSPEAKER (MAIN) AND HEADPHONE (AUXILIARY) OUTPUTS Vo(clip)(rms) Ro RL(AC) RL(DC) CoL Voffset(DC) mute clipping level output voltage (RMS value) output resistance AC load resistance DC load resistance output load capacitance static DC offset voltage mute suppression nominal input signal from any source; fi = 1 kHz; note 3 from any source fripple = 70 Hz; Vripple = 100 mV (peak); CVref = 47 F; signal from I2S-bus THD < 3% 1250 150 10 10 - - 80 1400 250 - - 10 30 - - 375 - - 12 70 - mV k k nF mV dB
Gro(main,aux)
roll-off gain at 14.5 kHz for Main and Auxiliary channels
-3 40
-2 45
- -
dB dB
PSRRmain,aux power supply ripple rejection for Main and Auxiliary channels SCART OUTPUTS AND LINE OUTPUT Vo(nom)(rms) Vo(clip)(rms) Ro RL(AC) RL(DC) CoL Voffset(DC) mute nominal level output voltage (RMS value) clipping level output voltage (RMS value) output resistance AC load resistance DC load resistance output load capacitance static DC offset voltage mute suppression
3 dB amplification; note 3 THD < 3%
- 1250 150 10 10 -
500 1400 250 - - - 30 -
- - 375 - - 2.5 50 -
mV mV k k nF mV dB
output amplifiers at 3 dB position nominal input signal from any source; fi = 1 kHz; note 3 from SCART, external and mono sources; -3 dB bandwidth from DSP sources; -3 dB bandwidth
- 80
B
bandwidth
20
-
-
kHz
14.5 40
- 45
- -
kHz dB
PSRR
power supply ripple rejection
fripple = 70 Hz; Vripple = 100 mV (peak); CVref = 47 F; signal from I2S-bus
1998 Aug 10
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
SYMBOL Audio performance THD + N
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
total harmonic distortion plus noise
Vi = Vo = 1 V (RMS); fi = 1 kHz; bandwidth 20 Hz to 15 kHz; note 8 from any analog audio input to I2S-bus from I2S-bus to any analog audio output SCART-to-SCART copy SCART-to-Main copy - - - - 0.1 0.1 0.1 0.2 0.3 0.3 0.3 0.5 % % % %
S/N
signal-to-noise ratio
reference voltage Vo = 1.4 V (RMS); fi = 1 kHz; "CCIR468"; quasi peak; note 8 from any analog audio input to I2S-bus from I2S-bus to any analog audio output SCART-to-SCART copy SCART-to-Main copy 73 78 78 73 70 65 65 60 -1.5 77 85 85 77 - - - - 0 - - - - - - - - +1.1 dB dB dB dB dB dB dB dB dB
ct
crosstalk attenuation
between any analog input pairs; fi = 1 kHz between any analog output pairs; fi = 10 kHz
cs
channel separation
between left and right of any input pair between left and right of any output pair
GA
gain from SCART-to-SCART output amplifier in 3 dB with -3 dB input voltage divider position; Rext = 15 k 10% output amplifier in 0 dB position; Rext = 15 k 10%
-4.5
-3.0
-1.9
dB
1998 Aug 10
25
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
SYMBOL
PARAMETER
CONDITIONS - - - - CL changed from 18 to 16 pF at nominal frequency - -
MIN.
TYP. - - - 7 -
MAX.
UNIT
Crystal specification (fundamental mode) fxtal CL C1 C0 pull crystal frequency load capacitance series capacitance parallel capacitance pulling sensitivity 24.576 20 20 - 25 - - +25 - - - MHz pF fF pF 10 ----------pF C 10-6 10-6 10 ----------year
-6 -6
RR RN T XJ XD XA
equivalent series resistance equivalent series resistance of unwanted mode temperature range adjustment tolerance drift ageing
30 - +70 30 30 5
2RR -20 - across temperature range - -
Notes 1. All analog and digital supply ground pins are connected internally. 2. Set demodulator to AM mode. Apply an AM carrier (with 1 kHz and 100%) to one channel. Check AGC step. Switch AGC off and set AGC to the gain step found. Measure the 1 kHz signal level of this channel and take it as a reference. Switch to the other SIF input to which no signal is connected and which is terminated with 50 . Measure now the 1 kHz crosstalk signal level. The SIF source resistance should be low (50 ). 3. Definitions of levels and level setting: The full-scale level for analog audio signals is VFS = 1.4 V (RMS). The nominal level at the digital crossbar switch is defined at -15 dB (full-scale). Nominal audio input levels: external, mono: 500 mV (RMS); -9 dB (full-scale). See also Tables 6 and 7. 4. FM source; in dual mode only A (respectively B) signal modulated; measured at B (respectively A) channel output; Vo = 1 V (RMS) of modulated channel. 5. FM source; in stereo mode only L (respectively R) signal modulated; measured at R (respectively L) channel output; Vo = 1 V (RMS) of modulated channel. The stereo channel separation may be limited by adjustment tolerances of the transmitter. 6. If the supply voltage for the TDA9870A is switched off, because of the ESD protection circuitry, all audio input pins are short-circuited. To avoid a short-circuit at the SCART inputs a 15 k resistor (-3 dB divider) has to be used. 7. The SCART specification allows a signal level of up to 2 V (RMS). Because of signal handling limitations due to the 5 V supply voltage for the TDA9870A, there is a need for fixed 3 dB attenuators at the SCART inputs. To achieve SCART-to-SCART copies with 0 dB gain, there are 3 dB and 0 dB amplifiers at the outputs of SCART 1 and SCART 2 and at the line output. The attenuator is realized by an internal resistor that works together with an external series resistor as a voltage divider. With this voltage divider the maximum SCART input signal level of 2 V (RMS) is scaled down to 1.4 V (RMS) at the input pin. To avoid clipping, the 3 dB gain must not be used if the SCART input signal is larger than 1.4 V (RMS). 8. ADC level adjust = 6 dB, all other level adjusts = 0 dB, if external -3 dB divider is used set output buffer gain to 3 dB, tone control to 0 dB, AVL off and volume control to 0 dB.
1998 Aug 10
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Digital TV Sound Processor (DTVSP)
IDENT on on on on on
SOURCE
SAT FM, stereo SAT FM, mono
Product specification
TDA9870A
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10 I2C-BUS CONTROL 10.1 Introduction 10.2 Power-up state
TDA9870A
At power-up the device is in the following state: * All outputs muted * No sound carrier frequency loaded * General purpose I/O pins ready for input (HIGH) * Input SIF1 selected with: - AGC on - Small hysteresis - SIF input level shift 0 dB. * Demodulators for both sound carriers set to FM with: - Identification for B/G, D/K, response time 1 s - Level adjust set to 0 dB - De-emphasis 50 s - Matrix set to mono. * Main channel set to FM input with: - Spatial off - Pseudo off - AVL off - Volume mute - Bass flat - Treble flat - Contour off - Bass boost flat. * Auxiliary channel set to FM input with: - Volume mute - Bass flat - Treble flat. * Feature interface all outputs off * Beeper off * Monitoring of carrier 1 FM demodulator DC output. After power-up a device initialization has to be performed via the I2C-bus to put the TDA9870A into the proper mode of operation, in accordance with the desired TV standard, audio control settings, etc.
The TDA9870A is fully controlled via the I2C-bus. Control is exercised by writing data to one or more internal registers. Status information can be read from an array of registers to enable the controlling microcontroller to determine whether any action is required. The device has an I2C-bus slave transceiver, in accordance with the fast-mode specification, with a maximum speed of 400 kbits/s. Information concerning the I2C-bus can be found in brochure "I2C-bus and how to use it" (order number 9398 393 40011). To avoid conflicts in a real application with other ICs providing similar or complementary functions, there are four possible slave addresses available which can be selected by pins ADDR1 and ADDR2 (see Table 8). Table 8 Possible slave addresses ADDR1 0 1 0 1 SLAVE ADDRESS A6 TO A0 1011000 1011001 1011010 1011011
ADDR2 0 0 1 1
The I2C-bus interface remains operational in the standby mode of the TDA9870A to allow control of the analog source selectors with regard to SCART-to-SCART copying. The device will not respond to a `general call' on the I2C-bus, i.e. when a slave address of 0000000 is sent by a master. The data transmission between the microcontroller and the other I2C-bus controlled ICs is not disturbed when the supply voltage of the TDA9870A is not connected.
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3 Slave receiver mode
TDA9870A
As a slave receiver, the TDA9870A provides 46 registers for storing commands and data. These registers are accessed via so-called subaddresses. A subaddress can be thought of as a pointer to an internal memory location. Table 9 S I2C-bus; slave address, subaddress and data format SLAVE ADDRESS 0 ACK SUBADDRESS ACK DATA ACK P
Table 10 Explanation of Table 9 BIT S SLAVE ADDRESS 0 ACK SUBADDRESS DATA P START condition 7-bit device address data direction bit (write to device) acknowledge by slave address of register to write to data byte to be written into register STOP condition FUNCTION
It is allowed to send more than one data byte per transmission to the TDA9870A. In this event, the subaddress is automatically incremented after each data byte, resulting in storing the sequence of data bytes at successive register locations, starting at SUBADDRESS. A transmission can start at any valid subaddress. Each byte is acknowledged with ACK (acknowledge). There is no `wrap-around' of subaddresses. Commands and data are processed as soon as they have been completely received. Functions requiring more than one byte will, thus, be executed only after all bytes for that function have been received. If the transmission is terminated (STOP condition) before all bytes have been received, the incomplete data for that function is ignored. Table 11 Format for a transmission employing auto-increment of subaddresses S Note 1. n data bytes with auto-increment of subaddresses. Data patterns sent to the various subaddresses are not checked for being illegal or not at that address, except for the functions of volume, bass, treble control, bass boost and level adjust. Detection of a STOP condition without a preceding acknowledge bit is regarded as a bus error. The last operation will not then be executed. SLAVE ADDRESS 0 ACK SUBADDRESS ACK DATA BYTE A(1) DATA ACK P
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
Table 12 Overview of the slave receiver registers SUBADDRESS (DECIMAL) MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 0 c p f f f f f f c d 0 0 0 0 0 0 0 m g 0 0 0 s 0 0 v v 0 0 0 0 v v 0 0 0 0 0 c 0 f f f f f f c d 0 0 0 0 0 0 0 m m g g g s m 0 v v 0 0 0 m v v 0 0 0 m s c 0 f f f f f f c d 0 0 0 0 0 0 0 m m m m m s m s v v 0 0 0 m v v 0 0 0 m DATA
TDA9870A
FUNCTION LSB g c m f f f f f f c d 0 l l 0 0 0 0 m m m m m l m s v v c b t m v v b t c m g c m f f f f f f c d 0 l l 0 0 0 0 m g 0 0 0 l 0 p v v c b t 0 v v b t c 0 g c s f f f f f f c d m l l 0 0 0 0 m s s s 0 l s p v v c b t s v v b t c s g c s f f f f f f c d m l l 0 0 0 0 m s s s 0 l s a v v c b t s v v b t c s g c s f f f f f f c d m l l 0 0 0 0 m s s s s l s a v v c b t s v v b t c s AGC level shift, AGC gain selection general configuration monitor select, peak detector on/off carrier 1 frequency; MS part carrier 1 frequency carrier 1 frequency; LS part carrier 2 frequency; MS part carrier 2 frequency carrier 2 frequency; LS part demodulator configuration FM de-emphasis FM matrix channel 1 output level adjust channel 2 output level adjust set to logic 0; note 1 set to logic 0; note 1 set to logic 0; note 1 set to logic 0; note 1 audio mute control DAC output select SCART 1 output select SCART 2 output select line output select ADC output select Main channel select audio effects (AVL, pseudo, spatial) volume control, Main left volume control, Main right contour control, Main bass control, Main treble control, Main Auxiliary channel select volume control, Auxiliary left volume control, Auxiliary right bass control, Auxiliary treble control, Auxiliary feature interface configuration I2S1 output select
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
SUBADDRESS (DECIMAL) MSB 38 39 40 41 42 43 44 45 Note 0 0 0 0 0 0 0 b 0 0 m 0 0 0 0 b 0 0 m 0 0 0 v b i
DATA FUNCTION LSB i o 0 i o 0 v b i o s i o f v b i o s i o f v b i o s i o f v b I2S1 input level adjust I2S1 output level adjust I2S2 output select I2S2 input level adjust I2S2 output level adjust beeper frequency beeper volume, Main and Auxiliary bass boost, Main left and right o m i o 0 v b
1. These bits have not been assigned to a function. The following sub-sections provide a detailed description of the slave receiver registers: 10.3.1 AGC GAIN REGISTER
10.3.1.1
Description
If the automatic gain control function is switched off in the general configuration register, the contents of this register will define a fixed gain of the AGC stage. The input voltages given are meant to generate a full scale output from the SIF ADC. If automatic gain control is on, the AGCGAIN setting is ignored. After switching off the automatic gain control function, the latest gain control setting is copied to the AGC gain register. If the AGC input level shift bit AGCLEV is set to HIGH the input signal is scaled with -10 dB. The AGCLEV bit is also active if the automatic gain function is enabled. It should be noted that the input voltages should be considered as approximate target values. Table 13 Description of the AGC gain register BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) NAME - - AGCLEV set to logic 0 set to logic 0 If the AGC input level shift bit AGCLEV is set to HIGH the input signal is scaled with -10 dB. The AGCLEV bit is also active if the automatic gain function is enabled. DESCRIPTION
AGCGAIN If the automatic gain control function is switched off in the general configuration register, the contents of this register will define a fixed gain of the AGC stage.
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.1.2 Definition
TDA9870A
Table 14 Subaddress 0 MSB B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1. The default setting at power-up is 00000000. B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 B4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 AGC GAIN SIF INPUT VOLTAGE (dB) (mV (p-p)) 0.0 0.8 1.5 2.3 3.1 3.9 4.6 5.4 6.2 7.0 7.7 8.5 9.3 10.1 10.8 11.6 12.4 13.2 13.9 14.7 15.5 16.3 17.0 17.8 18.6 19.4 20.1 20.9 21.7 22.5 23.2 24.0 941/2976 861/2723 788/2490 720/2278 659/2084 603/1906 551/1744 504/1595 461/1459 422/1334 386/1221 353/1117 323/1021 295/934 270/855 247/782 226/715 207/654 189/598 173/547 158/501 145/458 132/419 121/383 111/350 101/321 93/293 85/268 78/245 71/224 65/205 59/188 (note 1)
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.2 GENERAL CONFIGURATION REGISTER
TDA9870A
10.3.2.1
Description
Table 15 Description of Table 16 NAME SIFSEL AGCOFF HIGH/LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH FUNCTION Selects pin SIF2 for input (recommended for satellite tuner). Pin SIF1 (terrestrial TV) is selected. Forces the AGC block to a fixed gain as defined in the AGC gain register. The automatic gain control function is enabled and the contents of the AGC gain register is ignored. A longer decay time is selected for input signals with strong video modulation (intercarrier). This bit only has an effect when bit AGCOFF = 0. Selects normal attack and decay times for the AGC. Resets the power fail detector to LOW. This bit is automatically reset to LOW after bit POR in the device status register has been reset. Causes initialization of TDA9870A to its default settings. This has the same effect as a power-on reset. If there is a conflict between the default settings and any bit set HIGH in this register, the bits of this register have priority over the corresponding default setting. This bit is automatically reset to LOW after initialization. When set LOW, the TDA9870A is in its normal mode of operation. Puts the TDA9870A into the standby mode. Most functions are disabled and power dissipation is somewhat reduced, but the analog selectors/matrices remain operational to support analog copying from SCART-to-SCART and vice versa. The TDA9870A is in its normal mode of operation. On return from standby mode, the device is in its power-on reset mode and needs to be re-initialized. These bits control the general purpose input/output pins. The contents of these bits is written directly to the corresponding pins. If input is desired, the bits must be set HIGH to allow the pins to be pulled LOW externally. Input from the pins is reflected in the device status register (see Section 10.4, subaddress 0). P1OUT is recommended to be used for switching an SIF trap for the adjacent picture carrier in designs that employ such a trap.
AGCSLOW
CLRPOR
INIT
LOW STDBY HIGH
LOW P1OUT, P2OUT -
10.3.2.2
Definition
Table 16 Subaddress 1 (note 1) BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) Note 1. The default setting at power-up is 11000000. NAME P2OUT P1OUT STDBY INIT CLRPOR AGCSLOW AGCOFF SIFSEL DESCRIPTION general purpose I/O pin 2 general purpose I/O pin 1 standby mode on/off initialize to defaults (as reset) clear power-on reset flip-flop AGC decay time AGC on/off SIF input select
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.3 MONITOR SELECT REGISTER
TDA9870A
10.3.3.1
Description
This register is used to define the signal source, the level of which is to be monitored, and if the peak level is to be monitored. Peak level refers to the magnitude of the maximum excursion of a signal. Data can be read-out in the I2C-bus slave transmitter mode (see Section 10.4, subaddresses 5 and 6). Audio magnitude/phase is related to the FM demodulator output. Phase information is provided, when it operates in FM mode, while magnitude is supplied in AM mode. Table 17 Description of bit PEAKMON NAME PEAKMON HIGH/LOW HIGH LOW the last sample will be supplied FUNCTION selects the peak level of a source to be monitored
10.3.3.2
Definition
Table 18 Subaddress 2 (note 1) MSB B7 PEAKMON Note 1. The default setting at power-up is 00000000. Table 19 Signal source (note 1) B2 0 0 0 0 1 1 1 1 Note 1. The term `crossbar' refers to the digital selector, where level-adjusted signals from various sources are available. B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 SIGNAL SOURCE DC output of FM demodulator audio magnitude/phase, FM demodulator output crossbar input from FM/AM channel don't care crossbar input from I2S1 channel crossbar input from I2S2 channel crossbar input from audio ADC channel input to Main channel DAC (without beeper) B6 0 B5 0 B4 B3 B2 B1 see Table 19 see Table 20 LSB B0
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
Table 20 Monitor output B4 0 0 1 B3 0 1 0 MONITOR OUTPUT L input + R input -----------------------------------------2 L input (channel 1, respectively) R input (channel 2, respectively)
TDA9870A
10.3.4.2 Definition
Most significant part at subaddress 3. Table 21 Subaddresses 3 to 5 BIT 7 (MSB) 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 (LSB) 10.3.5 CARRIER 2 FREQUENCY REGISTER 5 4 3 SUBADDRESSES
10.3.3.3
Note
By reading out level read-out registers (subaddresses 5 and 6, see Section 10.4), the current peak level will be reset. 10.3.4 CARRIER 1 FREQUENCY REGISTER
10.3.4.1
Description
The three bytes together constitute a 24-bit frequency control word to represent the sound carrier (i.e. mixer) frequency in accordance with the following formula: f mix 24 data = -------- x 2 f clk Where: data = 24-bit frequency control word. fmix = desired sound carrier frequency. fclk = 12.288 MHz (clock frequency of mixer). 224 = 16777216 (number of steps in a 24-bit word size). Example: A 5.5 MHz sound carrier frequency will be generated by sending the following sequence of data bytes to the TDA9870A (data = 7509333 in decimal notation or 729555 in HEX): 01110010 10010101 01010101. As three bytes are required to define a carrier frequency, execution of this command starts only after all bytes have been received. If an error occurs, e.g. a premature STOP condition, partial data for this function is ignored. The default setting at power-up is 00000000 for all three bytes.
10.3.5.1
Description
Same as for sound carrier 1. If the carrier 2 frequency register is used, it will be for the second FM sound carrier of a terrestrial or satellite FM program.
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.5.2 Definition
TDA9870A
Subaddresses 6 to 8. Same as for sound carrier 1, except for subaddresses used. 10.3.6 DEMODULATOR CONFIGURATION REGISTER
10.3.6.1
Description
Table 22 Description of subaddress 9 (notes 1 and 2) NAME CH1MODE FILTBW0, FILTBW1 CH2MOD0, CH2MOD1 IDAREA IDMOD0, IDMOD1 Notes 1. It is recommended to switch the FM sound mode identification off whenever the received program is not a terrestrial 2-carrier sound. 2. Switching the identification off will reset the associated hardware to a defined state. HIGH/LOW HIGH LOW - - HIGH LOW - FUNCTION selects the hardware for the first sound carrier to operate in AM mode FM mode is assumed. This applies to both terrestrial and satellite FM reception. selects the filter bandwidth for channel 1 and channel 2 in accordance with Table 25 These bits control the hardware for the second sound carrier in accordance with the truth Table 24. selects FM identification frequencies in accordance with the specification for Korea frequencies for Europe are selected (B/G and D/K standard) These bits define the response time after which a sound mode identification result may be expected. The longer the time, the more reliable the identification.
10.3.6.2
Definition
Table 23 Subaddress 9 (note 1; see Table 22) BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) Note 1. The default setting at power-up is 00000000. NAME IDMOD1 IDMOD0 IDAREA FILTBW1 CH2MOD1 CH2MOD0 FILTBW0 CH1MODE selects filter bandwidth in accordance with Table 25 channel 1 receive mode application area for FM identification selects filter bandwidth in accordance with Table 25 channel 2 receive mode DESCRIPTION response time for FM sound mode identification
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
Table 24 Channel 2 receive mode (see Table 23) B3 0 0 1 B2 0 1 0
TDA9870A
CHANNEL 2 FM AM don't care
Table 25 Filter bandwidth Channel 1 and Channel 2 (see Table 23) FILTER BANDWIDTH B4 0 0 1 1 B1 CH1 0 1 0 1 narrow extra wide medium wide CH2 narrow narrow medium wide recommended for nominal terrestrial broadcast conditions and SAT with 2 carriers recommended only for high-deviation SAT mono carriers (e.g. obsolete main channel on Astra) recommended for moderately overmodulated broadcast conditions recommended for strongly overmodulated broadcast conditions FILTER MODES
Table 26 Identification mode (see Table 23) B7 0 0 1 1 10.3.7 FM DE-EMPHASIS REGISTER B6 0 1 0 1 IDENT MODE slow medium fast off/reset
10.3.7.1
Description
This register is used to select the proper de-emphasis characteristics as appropriate for the standard of the received carrier. Bits B3 to B0 apply to sound carrier 1, bits B7 to B4 apply to sound carrier 2. In the event of A2 reception, both groups must be set to the same characteristics.
10.3.7.2
Definition
Table 27 Subaddress 10 (note 1) BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) Note 1. The default setting at power-up is 00000000. 1998 Aug 10 37 NAME ADEEM2 DESCRIPTION adaptive de-emphasis on/off time constant selection for FM de-emphasis
ADEEM1
adaptive de-emphasis on/off time constant selection for FM de-emphasis
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
Table 28 De-emphasis B6, B2 0 0 0 0 1 B5, B1 0 0 1 1 0 B4, B0 0 1 0 1 0 50 s (Europe) 60 s 75 s (M standard) J17 off DE-EMPHASIS
TDA9870A
Table 29 Description of bits ADEEM1 and ADEEM2 (note 1) NAME ADEEM1, ADEEM2 Note 1. The FM de-emphasis gain is 0 dB at 40 Hz. 10.3.8 FM MATRIX REGISTER HIGH/LOW HIGH LOW FUNCTION Activates the adaptive de-emphasis function, which is required for certain satellite FM channels. The standard FM de-emphasis must then be set to 75 s. the adaptive de-emphasis is off
10.3.8.1
Description
This register is used to select the proper dematrixing characteristics as appropriate for the standard of the received carrier and the related sound mode identification.
10.3.8.2
Definition
Table 30 Subaddress 11 (notes 1) MSB B7 0 Note 1. The default setting at power-up is 00000000. B6 0 B5 0 B4 0 B3 0 B2 B1 see Table 31 LSB B0
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
Table 31 Description of Subaddress 11 (bits B2 to B0) B2 0 0 0 0 1 1 Notes 1. CH1: audio signal from FM channel 1. 2. CH2: audio signal from FM channel 2. 3. See Table 6. For stereo Korea the dematrix applies 6 dB attenuation. 10.3.9 FM CHANNEL 1 LEVEL ADJUST REGISTER B1 0 0 1 1 0 0 B0 0 1 0 1 0 1 L OUTPUT CH1 input; note 1 CH2 input; note 2 CH1 input; note 1 CH2 input; note 2 CH1 input + CH2 input ----------------------------------------------------------2 R OUTPUT CH1 input; note 1 CH2 input; note 2 CH2 input; note 2 CH1 input; note 1 CH1 input - CH2 input ---------------------------------------------------------2
TDA9870A
MODE mono 1 mono 2 dual dual swapped stereo Europe stereo Korea; note 3
2CH1 input - CH2 input CH2 input; note 2
10.3.9.1
Description
This register is used to correct for standard and station-dependent differences of signal levels. Table 32 applies to sound carrier 1.
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.9.2 Definition
TDA9870A
Table 32 Subaddress 12 MSB B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1. The default setting at power-up is 00000000. 10.3.10 FM CHANNEL 2 LEVEL ADJUST REGISTER B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 mute
10.3.10.1 Description
This register is used to correct for standard and station-dependent differences of signal levels. Table 33 applies to sound carrier 2 in its FM and AM modes. In the event of A2, channels 1 and 2 should be adjusted to the same level.
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.10.2 Definition
Table 33 Subaddress 13 MSB B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1. The default setting at power-up is 00000000. B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
TDA9870A
GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 mute
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.11 REGISTER 14 10.3.14 REGISTER 17
TDA9870A
10.3.11.1 Description
Set to logic 0. This bits have not been assigned to a function. 10.3.12 REGISTER 15
10.3.14.1 Description
Set to logic 0. This bits have not been assigned to a function. 10.3.15 AUDIO MUTE CONTROL REGISTER
10.3.12.1 Description
Set to logic 0. This bits have not been assigned to a function. 10.3.13 REGISTER 16
10.3.15.1 Description
When any of these bits are set HIGH, the corresponding pair of output channels will be muted. A LOW bit allows normal signal output. There is a soft-mute facility for the Main and Auxiliary output channels to provide click-free muting independent of the volume control. This is switched on/off by bits MUTMAIN and MUTAUX.
10.3.13.1 Description
Set to logic 0. This bits have not been assigned to a function.
10.3.15.2 Definition
Table 34 Subaddress 18 (note 1) BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) Note 1. The default setting at power-up is 11111111. 10.3.16 DAC OUTPUT SELECT REGISTER NAME MUTI2S2 MUTI2S1 MUTDAC MUTLINE MUTSC2 MUTSC1 MUTAUX MUTMAIN DESCRIPTION mute I2S2 outputs mute I2S1 outputs mute internal DAC mute line outputs mute SCART 2 outputs mute SCART 1 outputs mute Auxiliary outputs mute Main channels
10.3.16.1 Description
This register is used to define both the signal source to be entered into the DAC and the mode of the digital matrix for signal selection. The DAC is used for signal output from digital sources at analog outputs. The bits DACGAIN1 and DACGAIN2 can introduce some extra gain at the input to the DAC. DACGAIN1 adds 3 dB and DACGAIN2 adds 6 dB of gain, respectively.
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.16.2 Definition
Table 35 Subaddress 19 (note 1) MSB B7 DACGAIN2(2) Notes 1. The default setting at power-up is 00000000. 2. See Table 38. Table 36 Signal source left and right B6 B5 see Table 37 B4 B3 DACGAIN1(2) B2 B1
TDA9870A
LSB B0 see Table 36
SIGNAL SOURCE B2 0 0 0 0 1 1 1 1 Table 37 Bits B6 to B4 B6 0 0 0 0 1 B5 0 0 1 1 0 B4 0 1 0 1 0 L OUTPUT L input L input R input R input L+R ------------2 R OUTPUT R input L input R input L input L+R ------------2 B1 0 0 1 1 0 0 1 1 B0 LEFT 0 1 0 1 0 1 0 1 I2S1 left I2S2 left ADC left AVL left don't care don't care FM left don't care I2S1 right I2S2 right ADC right AVL right RIGHT FM right
Table 38 Description of bits DACGAIN1 and DACGAIN2 B7 0 0 1 1 B3 0 1 0 1 GAIN (dB) 0 3 6 9
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.17 SCART 1 OUTPUT SELECT REGISTER
TDA9870A
10.3.17.1 Description
This register is used to define both the signal source to be output at SCART 1 and the output channel selector mode.
10.3.17.2 Definition
Table 39 Subaddress 20 (note 1) MSB B7 0 Notes 1. The default setting at power-up is 00000001. 2. See Table 42. Table 40 Signal source B2 0 0 0 0 1 Table 41 Bits B5 and B4 B5 0 0 1 1 Table 42 Description of bit SC1GAIN NAME SC1GAIN HIGH/LOW HIGH FUNCTION Activates the 3 dB gain stage at the SCART 1 output buffers. As any SCART input passes a 3 dB attenuator, this gain stage can be used to compensate that attenuation, resulting in a 0 dB insertion loss when copying from SCART 2 input to SCART 1 output. However, that gain must be used with great care, as it will cause signal clipping at high input levels. The audio signal will be output unchanged (0 dB gain). B4 0 1 0 1 L OUTPUT L input L input R input R input R OUTPUT R input L input R input L input B1 0 0 1 1 0 B0 0 1 0 1 0 SIGNAL SOURCE SCART 1 input SCART 2 input external input mono input DAC input B6 SC1GAIN(2) B5 B4 B3 0 B2 B1 see Table 40 see Table 41 LSB B0
LOW
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.18 SCART 2 OUTPUT SELECT REGISTER
TDA9870A
10.3.18.1 Description
This register is used to define both the signal source to be output at SCART 2 and the output channel selector mode.
10.3.18.2 Definition
Table 43 Subaddress 21 (note 1) MSB B7 0 Notes 1. The default setting at power-up is 00000000. 2. See Table 46. Table 44 Signal source B2 0 0 0 0 1 Table 45 Bits B5 and B4 B5 0 0 1 1 Table 46 Description of bit SC2GAIN NAME SC2GAIN HIGH/LOW HIGH FUNCTION Activates the 3 dB gain stage at the SCART 2 output buffers. As any SCART input passes a 3 dB attenuator, this gain stage can be used to compensate that attenuation, resulting in a 0 dB insertion loss when copying from SCART 1 input to SCART 2 output. However, that gain must be used with great care, as it will cause signal clipping at high input levels. The audio signal will be output unchanged (0 dB gain). B4 0 1 0 1 L OUTPUT L input L input R input R input R OUTPUT R input L input R input L input B1 0 0 1 1 0 B0 0 1 0 1 0 SIGNAL SOURCE SCART 1 input SCART 2 input external input mono input DAC input B6 SC2GAIN(2) B5 B4 B3 0 B2 B1 see Table 44 see Table 45 LSB B0
LOW
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.19 LINE OUTPUT SELECT REGISTER
TDA9870A
10.3.19.1 Description
By definition, the line output conveys the same signal as the Main (loudspeaker) channel, but in a non-processed form. This register is used to characterize the signal to be output at the line output and define the output channel selector mode.
10.3.19.2 Definition
Table 47 Subaddress 22 (note 1) BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) Note 1. The default setting at power-up is 00000000. Table 48 Bits B5 and B4 B5 0 0 1 1 B4 0 1 0 1 L OUTPUT L input L input R input R input R OUTPUT R input L input R input L input - - - LINSEL set to logic 0 set to logic 0 set to logic 0 select source for line output; see Table 49 NAME - LINGAIN DESCRIPTION set to logic 0 line output gain on/off; see Table 49 see Table 48
Table 49 Description of bits LINSEL and LINGAIN NAME LINSEL HIGH/LOW HIGH FUNCTION Specifies that a signal from an analog source is being processed in the Main channel. Analog signal sources comprise SCART 1 input, SCART 2 input, external input and mono input, i.e. any input to the ADC. Specifies that a signal from a digital source is being processed in the Main channel. Digital signal sources comprise FM, I2S1 input and I2S2 input. Activates the 3 dB gain stage at the line output buffers. The audio signal will be output unchanged (0 dB gain).
LOW LINGAIN HIGH LOW
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.20 ADC OUTPUT SELECT REGISTER
TDA9870A
10.3.20.1 Description
This register is used to define the signal source for the ADC. There is no output channel selector, because all digital signal sinks of the ADC have their own matrix. Instead, a level adjustment facility for the ADC output is provided.
10.3.20.2 Definition
Table 50 Subaddress 23 (note 1) MSB B7 B6 see Table 51 Note 1. The default setting at power-up is 00000000. Table 51 Signal source B7 0 0 0 0 B6 0 0 1 1 B5 0 1 0 1 SIGNAL SOURCE SCART 1 input SCART 2 input external input mono input B5 B4 B3 B2 see Table 52 B1 LSB B0
1998 Aug 10
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
Table 52 ADC level adjust (note 1) B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
TDA9870A
GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 mute
1. If the ADC level adjust is set to 0 dB a full-scale input signal to the ADC results into a level of -6 dB full-scale at the digital x-bar.
1998 Aug 10
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.21 MAIN CHANNEL SELECT REGISTER
TDA9870A
10.3.21.1 Description
This register is used to define both the signal source to be processed in the Main (loudspeaker) channel and the mode of the digital matrix for signal selection.
10.3.21.2 Definition
Table 53 Subaddress 24 (note 1) MSB B7 0 Note 1. The default setting at power-up is 00000000. Table 54 Signal source B2 0 0 0 0 1 Table 55 Bits B6 to B4 B6 0 0 0 0 1 B5 0 0 1 1 0 B4 0 1 0 1 0 L OUTPUT L input L input R input R input L+R ------------2 R OUTPUT R input L input R input L input L+R ------------2 B1 0 0 1 1 0 B0 0 1 0 1 0 SIGNAL SOURCE FM input don't care I2S1 input I2S2 input ADC input B6 B5 see Table 55 B4 B3 0 B2 B1 see Table 54 LSB B0
1998 Aug 10
49
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.22 AUDIO EFFECTS REGISTER
TDA9870A
10.3.22.1 Definition
Table 56 Subaddress 25 (note 1; see Table 60) MSB B7 0 Notes 1. The default setting at power-up is 00000000. 2. See Table 59. 3. See Table 58. 4. See Table 57. Table 57 AVL control mode B1 0 0 1 1 Table 58 Pseudo control setting B3 0 0 1 1 Table 59 Spatial control setting B5 0 0 1 1 B4 0 1 0 1 SPATIAL SETTING (%) off 30 40 52 B2 0 1 0 1 PSEUDO SETTING (Hz) off 300 200 150 B0 0 1 0 1 AVL MODE off/reset short decay medium decay long decay B6 0 B5 SPATIAL1(2) B4 B3 B2 B1 AVL1(4) SPATIAL0(2) PSEUDO1(3) PSEUDO0(3) LSB B0 AVL0(4)
1998 Aug 10
50
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
Table 60 Description of Table 56 (notes 1, 2 and 3) NAME FUNCTION
TDA9870A
AVL0, AVL1 these bits set the mode of operation of the automatic volume level control function at the entrance to the Main (loudspeaker) channel PSEUDO0, PSEUDO1 SPATIAL0, SPATIAL1 Notes 1. Switching the AVL off will reset the associated hardware to a defined state. 2. When the signal source for the Main channel is changed while the AVL is on, the AVL needs to be reset in order to avoid excessive settling times. This can be achieved by switching the AVL off and on again. 3. The pseudo stereo function is based on an all-pass filter. A 90 degrees phase shift occurs at the frequencies stated in Table 58. There is a gain of 3 dB in the left audio channel. 10.3.23 VOLUME CONTROL REGISTERS (MAIN) These bits set the amount of the effect function (pseudo stereo) for mono signals in the Main channel. This function should be activated only in accordance with the result of the sound mode identification. These bits set the amount of the effect function (stereo base width expansion) for stereo signals in the Main channel. This function should be activated only in accordance with the result of the sound mode identification.
10.3.23.1 Description
These two registers control the volume setting of the Main (loudspeaker) channel. The register at subaddress 26 applies to the left channel signal, while the register at subaddress 27 applies to the right channel signal. Balance control is exercised by offsetting the left and right channel volume settings.
10.3.23.2 Definition
Table 61 Subaddresses 26 and 27 MSB B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1998 Aug 10 B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 B3 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 B2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 51 B1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 LSB VOLUME SETTING (dB) B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
MSB B7 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B6 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B5 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B4 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 B2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 B1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
LSB VOLUME SETTING (dB) B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 +8 +7 +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30
1998 Aug 10
52
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
MSB B7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 B5 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 B4 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 B3 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 B2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
LSB VOLUME SETTING (dB) B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -31 -32 -33 -34 -35 -36 -37 -38 -39 -40 -41 -42 -43 -44 -45 -46 -47 -48 -49 -50 -51 -52 -53 -54 -55 -56 -57 -58 -59 -60 -61 -62 -63 -64 -65 -66 -67 -68 -69
1998 Aug 10
53
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
MSB B7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1. The default setting at power-up is 10101100. B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B4 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 B3 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 B2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
LSB VOLUME SETTING (dB) B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 -70 -71 -72 -73 -74 -75 -76 -77 -78 -79 -80 -81 -82 -83 mute (note 1)
1998 Aug 10
54
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.24 CONTOUR CONTROL REGISTER
TDA9870A
10.3.24.1 Description
This register is used to apply the contour or loudness function (physiological volume control) to the left and right signal channels of the Main channel by means of an extra bass boost. The gain setting must be chosen in accordance with the volume control setting for the Main channel. For example, the contour gain could be incremented for every 5 dB, or so, of decrease of the volume setting. This needs to be done by the microcontroller. The 0 dB contour setting is equal to contour off.
10.3.24.2 Definition
Table 62 Subaddress 28 MSB B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1. The default setting at power-up is 00000000. B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB CONTOUR GAIN (dB) B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (note 1)
1998 Aug 10
55
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.25 BASS CONTROL REGISTER (MAIN)
TDA9870A
10.3.25.1 Description
This register is used to apply bass control to the left and right signal channels of the Main channel.
10.3.25.2 Definition
Table 63 Subaddress 29 MSB B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1. The default setting at power-up is 00000000. B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB BASS SETTING (dB) B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12
1998 Aug 10
56
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.26 TREBLE CONTROL REGISTER (MAIN)
TDA9870A
10.3.26.1 Description
This register is used to apply treble control to the left and right signal channels of the Main channel.
10.3.26.2 Definition
Table 64 Subaddress 30 MSB B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1. The default setting at power-up is 00000000. B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 B2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB TREBLE SETTING (dB) B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12
1998 Aug 10
57
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.27 AUXILIARY CHANNEL SELECT REGISTER
TDA9870A
10.3.27.1 Description
This register is used to define both the signal source to be processed in the Auxiliary (headphone) channel and the mode of the digital matrix for signal selection.
10.3.27.2 Definition
Table 65 Subaddress 31 (note 1) MSB B7 0 Note 1. The default setting at power-up is 00000000. Table 66 Signal source B2 0 0 0 0 1 1 Table 67 Bits B6 to B4 B6 0 0 0 0 1 B5 0 0 1 1 0 B4 0 1 0 1 0 L OUTPUT L input L input R input R input L+R ------------2 R OUTPUT R input L input R input L input L+R ------------2 B1 0 0 1 1 0 0 B0 0 1 0 1 0 1 SIGNAL SOURCE FM input don't care I2S1 input I2S2 input ADC input AVL input B6 B5 see Table 67 B4 B3 0 B2 B1 see Table 66 LSB B0
1998 Aug 10
58
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.28 VOLUME CONTROL REGISTERS (AUXILIARY)
TDA9870A
10.3.28.1 Description
These two registers control the volume setting of the Auxiliary (headphone) channel. The register at subaddress 32 applies to the left channel signal, while the register at subaddress 33 applies to the right channel signal. Balance control is exercised by offsetting the left and right channel volume settings.
10.3.28.2 Definition
Table 68 Subaddresses 32 and 33 MSB B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 B4 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 B3 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 B2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 B1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 LSB B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOLUME SETTING (dB) +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7
1998 Aug 10
59
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
MSB B7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
LSB B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VOLUME SETTING (dB) -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 -35 -36 -37 -38 -39 -40 -41 -42 -43 -44 -45 -46 -47 -48
1998 Aug 10
60
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
MSB B7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1. The default setting at power-up is 10101100. B6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VOLUME SETTING (dB) -49 -50 -51 -52 -53 -54 -55 -56 -57 -58 -59 -60 -61 -62 -63 -64 -65 -66 -67 -68 -69 -70 -71 -72 -73 -74 -75 -76 -77 -78 -79 -80 -81 -82 -83 mute (note 1)
1998 Aug 10
61
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.29 BASS CONTROL REGISTER (AUXILIARY)
TDA9870A
10.3.29.1 Description
This register is used to apply bass control to the left and right signal channels of the Auxiliary channel.
10.3.29.2 Definition
Table 69 Subaddress 34 MSB B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1. The default setting at power-up is 00000000. B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 BASS SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12
1998 Aug 10
62
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.30 TREBLE CONTROL REGISTER (AUXILIARY)
TDA9870A
10.3.30.1 Description
This register is used to apply treble control to the left and right signal channels of the Auxiliary channel.
10.3.30.2 Definition
Table 70 Subaddress 35 MSB B7 X X X X X X X X X X X X X X X X X X X X X X X X X Note 1. The default setting at power-up is 00000000. B6 X X X X X X X X X X X X X X X X X X X X X X X X X B5 X X X X X X X X X X X X X X X X X X X X X X X X X B4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 B2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 TREBLE SETTING (dB) +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12
1998 Aug 10
63
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.31 FEATURE INTERFACE CONFIGURATION REGISTER
TDA9870A
10.3.31.1 Definition
Table 71 Subaddress 36 (note 1) MSB B7 0 Notes 1. The default setting at power-up is 00000000. 2. System clock frequency select; see Table 72. 3. System clock output on/off; see Table 73. 4. Serial output format; see Table 73. 5. I2S-bus outputs on/off; see Table 73. Table 72 System clock frequency select B4 0 0 1 1 Note 1. With 16.384 MHz, the duty cycle is 33% : 67%. Table 73 Description of Table 71 NAME I2SOUT HIGH/LOW HIGH LOW I2SFORM HIGH LOW SYSOUT HIGH LOW FUNCTION Enables the output of serial audio data (2 pins) plus serial bit clock and word select in a format determined by the I2SFORM bit. The TDA9870A is then an I2S-bus master. the outputs mentioned will be 3-stated, thereby improving the EMC performance an MSB-aligned, MSB-first output format is selected, i.e. a level change at the word select pin indicates the beginning of a new audio sample the standard I2S-bus output format is selected enables the output of a system (or master) clock signal at pin SYSCLK the output will be off, thereby improving the EMC performance B3 0 1 0 1 SYSCLK OUTPUT 256fs 384fs 512fs 768fs FREQUENCY (MHz) 8.192 12.288 16.384; note 1 24.576 B6 0 B5 0 B4 SYSCL1(2) B3 SYSCL0(2) B2 SYSOUT(3) B1 I2SFORM(4) LSB B0 I2SOUT(5)
1998 Aug 10
64
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.32 I2S1 OUTPUT SELECT REGISTER
TDA9870A
10.3.32.1 Description
This register is used to define both the signal source to be output at I2S1 and the mode of the digital matrix for signal selection.
10.3.32.2 Definition
Table 74 Subaddress 37 (note 1) MSB B7 0 Note 1. The default setting at power-up is 00000000. Table 75 Signal source (note 1) B2 0 0 0 0 1 1 1 1 Note 1. The Main and Auxiliary channel outputs will not contain the beeper signal. Table 76 Bits B6 to B4 B6 0 0 0 0 1 B5 0 0 1 1 0 B4 0 1 0 1 0 L OUTPUT L input L input R input R input L+R ------------2 R OUTPUT R input L input R input L input L+R ------------2 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 SIGNAL SOURCE FM output don't care I2S1 input I2S2 input ADC output AVL output Auxiliary output Main output B6 B5 see Table 76 B4 B3 0 B2 B1 see Table 75 LSB B0
1998 Aug 10
65
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.33 I2S1 INPUT LEVEL ADJUST REGISTER
TDA9870A
10.3.33.1 Description
This register is used to adjust the input level at the I2S1 interface. Left and right signal channel are treated identically.
10.3.33.2 Definition
Table 77 Subaddress 38 MSB B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1. The default setting at power-up is 00000000. B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 mute
1998 Aug 10
66
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.34 I2S1 OUTPUT LEVEL ADJUST REGISTER
TDA9870A
10.3.34.1 Description
This register is used to adjust the output level at the I2S1 interface. Left and right signal channel are treated identically.
10.3.34.2 Definition
Table 78 Subaddress 39 MSB B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1. The default setting at power-up is 00000000. B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 mute
1998 Aug 10
67
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.35 I2S2 OUTPUT SELECT REGISTER
TDA9870A
10.3.35.1 Description
This register is used to define both the signal source to be output at I2S2 and the mode of the digital matrix for signal selection.
10.3.35.2 Definition
Table 79 Subaddress 40 (note 1) MSB B7 0 Note 1. The default setting at power-up is 00000000. Table 80 Signal source (note 1) B2 0 0 0 0 1 1 1 1 Note 1. The Main and Auxiliary channel outputs will not contain the beeper signal. Table 81 Bits B6 to B4 B6 0 0 0 0 1 B5 0 0 1 1 0 B4 0 1 0 1 0 L OUTPUT L input L input R input R input L+R ------------2 R OUTPUT R input L input R input L input L+R ------------2 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 SIGNAL SOURCE FM output don't care I2S1 input I2S2 input ADC output AVL output Auxiliary output Main output B6 B5 see Table 81 B4 B3 0 B2 B1 see Table 80 LSB B0
1998 Aug 10
68
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.36 I2S2 INPUT LEVEL ADJUST REGISTER
TDA9870A
10.3.36.1 Description
This register is used to adjust the input level at the I2S2 interface. Left and right signal channel are treated identically.
10.3.36.2 Definition
Table 82 Subaddress 41 MSB B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1. The default setting at power-up is 00000000. B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 mute
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.37 I2S2 OUTPUT LEVEL ADJUST REGISTER
TDA9870A
10.3.37.1 Description
This register is used to adjust the output level at the I2S2 interface. Left and right signal channel are treated identically.
10.3.37.2 Definition
Table 83 Subaddress 42 MSB B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1. The default setting at power-up is 00000000. B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 mute
1998 Aug 10
70
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.38 BEEPER FREQUENCY CONTROL REGISTER
TDA9870A
10.3.38.1 Description
This register is used to select from sample beeper oscillator frequencies. The beeper output signal is added to the Main and Auxiliary channel output DAC. Due to the frequency response of the audio DACs upsampling filters, the 25 kHz beep is approximately 5 dB louder than the 390 Hz beep.
10.3.38.2 Definition
Table 84 Subaddress 43 (note 1) MSB B7 0 0 0 0 0 0 0 0 Note 1. The default setting at power-up is 00000000. 10.3.39 BEEPER VOLUME CONTROL REGISTER B6 0 0 0 0 0 0 0 0 B5 0 0 0 0 0 0 0 0 B4 0 0 0 0 0 0 0 0 B3 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 LSB GENERATED FREQUENCY (Hz) B0 1 0 1 0 1 0 1 0 25000 7040 3580 1770 1270 900 640 390
10.3.39.1 Description
This register is used to set the beeper volume. The gain setting is relative to digital full scale at the input to the Main and Auxiliary channel output DACs. The beeper volume is independent of any other volume setting. The beeper signal is added to the Main and Auxiliary channel output signals in the 2 x fs domain. The beeper volume should be set with great care, when the audio signals in the Main and Auxiliary channels are close to digital full-scale, to avoid output signal distortion due to overload.
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.39.2 Definition
Table 85 Subaddress 44 MSB B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1. The default setting at power-up is 00100000. B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B4 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
TDA9870A
GAIN SETTING (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 -51 -54 -57 -60 -63 -66 -69 -72 -75 -78 -81 -84 -87 -90 -93 mute (note 1)
1998 Aug 10
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.3.40 BASS BOOST CONTROL REGISTER
TDA9870A
10.3.40.1 Description
This register is used to select from a few sample bass boost settings to modify the frequency characteristics of the Main channel (shelving filter). Bits B3 to B0 apply to the left channel, bits B7 to B4 apply to the right channel. This function must be used with care in order to avoid clipping distortion at high volume settings. More sophisticated control of the bass boost filter can be exercised in the expert mode (see Section 10.5). The user then has full control over this 2nd-order filter and can, within limits, realize bass equalizers with arbitrary centre frequencies, Q factors and boost/cut settings.
10.3.40.2 Definition
Table 86 Subaddress 45 (note 1; see Table 87) MSB B7 Note 1. The default setting at power-up is 00000000. Table 87 Gain setting B7 AND B3 1 1 1 0 0 0 0 0 0 0 0 B6 AND B2 0 0 0 1 1 1 1 0 0 0 0 B5 AND B1 1 0 0 1 1 0 0 1 1 0 0 B4 AND B0 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) 20 18 16 14 12 10 8 6 4 2 0 CORNER FREQUENCY (Hz) 350 350 350 350 350 350 350 350 350 350 350 B6 B5 B4 B3 B2 B1 LSB B0
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.4 Slave transmitter mode
TDA9870A
As a slave transmitter, the TDA9870A provides 13 registers with status information and data, a part of which is for Philips internal purposes only. These registers can be accessed by means of subaddresses. Table 88 General format for reading data from the TDA9870A S SLAVE ADDRESS 0 ACK SUBADDRESS ACK Sr SLAVE ADDRESS 1 ACK DATA NAm P
Table 89 Explanation of Tables 88 and 90 BIT S SLAVE ADDRESS 0 ACK SUBADDRESS Sr 1 DATA NAm Am P START condition 7-bit device address data direction bit (write to device) acknowledge (by the slave) address of register to read from repeated START condition data direction bit (read from device) data byte read from register not acknowledge (by the master) acknowledge (by the master) STOP condition FUNCTION
Reading of data can start at any valid subaddress. It is allowed to read more than 1 data byte per transmission from the TDA9870A. In this situation, the subaddress is automatically incremented after each data byte, which results in reading the sequence of data bytes from successive register locations, starting at SUBADDRESS. Table 90 Format of a transmission using automatic incrementing of subaddresses S SLAVE ADDRESS 0 ACK SUBADDRESS ACK Sr SLAVE ADDRESS 1 ACK DATA BYTE Am(1) DATA NAm P
Note 1. n data bytes with auto-increment of subaddresses. Each data byte in a read sequence, except for the last one, is acknowledged with Am (acknowledge by the master). The subaddresses `wrap around' from decimal 255 to 0. If an attempt is made to read from a non-existing subaddress, the device will send a data pattern of all ones, i.e. FF in hexadecimal notation.
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
Table 91 Overview of the slave transmitter registers (note 1) SUBADDRESS (DECIMAL) MSB 0 1 2 3 4 5 6 7 251 252 253 254 255 Notes s X X X X l l X a a a d s s X X X X l l X a a a d s X X X X X l l X a a a d s DATA
TDA9870A
FUNCTION LSB X X X X X l l c a a a d s X X X X X l l c a a a d s s X X X X l l c a a a d s s X X X X l l c a a a d s s X X X X l l c a a a d s device status (power-on, identification, etc.) don't care; note 1 don't care; note 1 don't care; note 1 don't care; note 1 level read-out (MSB) level read-out (LSB) SIF level test register 3; note 2 test register 2; note 2 test register 1; note 2 device identification code software identification code
1. X indicates a bit that has not been assigned to a function. This bit is reserved for future extensions. 2. Registers from subaddress 251 to 255 are for Philips internal purposes only. They are considered as a set of registers for the identification of individual members and some key parameters in a family of devices. A detailed description of the slave transmitter registers is given in below. 10.4.1 DEVICE STATUS REGISTER
10.4.1.1
Description
Table 92 Description of Table 93 NAME POR HIGH/LOW - FUNCTION The power supply for the digital part of the device, VDDD2, has temporarily been lower than the specified lower limit. If this is detected an initialization of the TDA9870A has to be carried out to ensure reliable operation. this bit is HIGH if an FM stereo signal has been identified This bit is HIGH if an FM dual-language signal has been identified. When neither IDSTE nor IDDUA are set, the received signal has to be assumed to be FM mono. these bits reflect the status of the corresponding general purpose port pins, see Section 10.3.2
IDSTE IDDUA P1IN, P2IN
- - -
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
10.4.1.2 Definition
TDA9870A
Table 93 Subaddress 0 BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) 10.4.2 REGISTER 1 NAME P2IN P1IN - - - IDDUA IDSTE POR DESCRIPTION input from port 2 input from port 1 don't care don't care don't care identification of FM dual sound identification of FM stereo power fail bit
10.4.6.2
Definition
10.4.2.1
Description
Table 94 Subaddress 5 BIT 7 (most significant bit or sign bit) 6 5 4 3 2 1 0 Table 95 Subaddress 6 BIT
Subaddress 1: These bits have not been assigned to a function. These bits are reserved for future extensions. 10.4.3 REGISTER 2
10.4.3.1
Description
Subaddress 2: These bits have not been assigned to a function. These bits are reserved for future extensions. 10.4.4 REGISTER 3
10.4.4.1
Description
Subaddress 3: These bits have not been assigned to a function. These bits are reserved for future extensions. 10.4.5 REGISTER 4
7 6 5 4 3 2 1 0 (least significant bit) 10.4.7 SIF LEVEL REGISTER
10.4.5.1
Description
Subaddress 4: These bits have not been assigned to a function. These bits are reserved for future extensions. 10.4.6 LEVEL READ-OUT REGISTERS
10.4.6.1
Description
These two bytes constitute a word that provides data from a location that has been specified with the monitor select register. The most significant byte of the data is stored at subaddress 5. If peak-level monitoring has been selected, the peak-level monitoring register is cleared and monitoring resumes after its contents has been transferred to these two bytes.
10.4.7.1
Description
When the SIF AGC is on, bits B4 to B0 of this register contain a number that gives an indication of the SIF input level. That number corresponds to the AGC gain register setting (see Section 10.3, subaddress 0).
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
When the SIF AGC is off, this register returns the contents of the AGC gain register. 10.4.11 DEVICE IDENTIFICATION CODE
TDA9870A
10.4.11.1 Description
There will be several devices in the digital TV sound processor family. This byte is used to identify the individual family members.
10.4.7.2
Definition
Table 96 Subaddress 7 MSB B7 10.4.8 B6 B5 B4 B3 B2 B1 LSB B0
10.4.11.2 Definition
Table 100 Subaddress 254
TEST REGISTER 3
MSB B7 0 B6 0 B5 1 B4 0 B3 0 B2 0 B1 1
LSB B0 0
10.4.8.1
Description
This register contains, as a binary number, the highest memory address used for the Coefficient RAM (CRAM, expert mode).
10.4.12 SOFTWARE IDENTIFICATION CODE
10.4.8.2
Definition
10.4.12.1 Description
It is likely that during the life time of this family of devices several versions of the DSP software will be made, e.g., to accommodate new application concepts, respond to customer wishes, etc. This byte is used to identify the different releases.
Table 97 Subaddress 251 MSB B7 0 10.4.9 B6 1 B5 1 B4 1 B3 1 B2 1 B1 1 LSB B0 1
TEST REGISTER 2
10.4.12.2 Definition
Table 101 Subaddress 255 MSB B7 0 B6 0 B5 0 B4 0 B3 0 B2 0 B1 1 LSB B0 0
10.4.9.1
Description
This register contains, as a binary number, the highest subaddress used for slave receiver registers.
10.4.9.2
Definition
10.5 LSB B6 0 B5 1 B4 0 B3 1 B2 1 B1 0 B0 1 Expert mode In addition to the slave receiver and slave transmitter modes previously described, there is a special `expert' mode that gives direct write access to the internal CRAM of the DSP. In this mode, transferred data contain 12-bit-wide coefficients. As those coefficients bypass on-chip coefficient look-up tables for many functions, they directly influence the processing of signals within the DSP. This mode must be used with great care. It can be used to create user-defined characteristics, such as a tone control with different corner frequencies or special boost/cut characteristics to correct the low-frequency loudspeaker and/or cabinet frequency responses.
Table 98 Subaddress 252 MSB B7 0
10.4.10 TEST REGISTER 1
10.4.10.1 Description
This register contains, as a binary number, the highest subaddress used for slave transmitter (status) registers.
10.4.10.2 Definition
Table 99 Subaddress 253 MSB B7 0 B6 0 B5 0 B4 0 B3 0 B2 1 B1 1 LSB B0 1
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
Table 102 General format for entering the expert mode and writing coefficients into the TDA9870A S SLAVE ADDRESS 0 ACK 10000000 ACK CRAM ADDRESS ACK DATA ACK
TDA9870A
DATA
ACK
P
Table 103 Explanation of Table 102 BIT S SLAVE ADDRESS 0 ACK 10000000 CRAM ADDRESS DATA P START condition 7-bit device address data direction bit (write to device) acknowledge pattern to enter the expert mode start address of coefficient RAM to write to data byte containing part of a coefficient STOP condition FUNCTION
As the coefficients do not fit into one data byte, they have to be split and arranged (see Table 104). The most significant bit is transferred first. Table 104 General format (notes 1, 2 and 3) BYTE 1. data byte 2. data byte Notes 1. X = don't care. 2. MST = most significant third. 3. LST = least significant third. The general format described in Table 104 shows the minimum number of data bytes required, i.e. two bytes for the transfer of a single coefficient. Should more than one coefficient be sent, then the CRAM address will be automatically incremented after each coefficient, resulting in writing the sequence of coefficients into successive memory locations, starting at CRAM ADDRESS. A transmission can start with any valid CRAM address. If two coefficients are to be transferred, they are arranged as shown in Table 105. Table 105 Transfer of two coefficients BYTE 1 data byte 2 data byte 3 data byte a a b a a b a a b DATA a a b a b b a b b a b b a b b DESCRIPTION 2 MST of 1st coefficient 1 LST of 1st coefficient + 1 MST of 2nd coefficient 2 LST of 2nd coefficient a a a a a a DATA a a a X a X a X a X DESCRIPTION 2 MST of 1st coefficient 1 LST of 1st coefficient
With any odd number of coefficients to be transferred, the least significant nibble of the last byte is regarded as containing don't care data.
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
As the transfer of coefficients cannot be accomplished within one audio sample period, it is necessary that received coefficients be buffered and made active all at the same time to avoid audio signal transients. The receive buffer is designed to store up to 8 coefficients in addition to the CRAM address. Each byte that fits into the buffer is acknowledged with ACK (acknowledge). If an attempt is made to write more coefficients than the buffer can store, the device acknowledges with NACK (not acknowledge) and any further coefficients are ignored. Coefficients that are already in the receive buffer remain intact. An expert mode transfer ends when the I2C-bus STOP condition or a repeated START condition has been detected. Only those coefficients that have been received during the last transmission will then be copied from the buffer to the CRAM. To make efficient and correct use of the expert mode, it is recommended to transfer all coefficients for any one function in a single transmission. There is no checking of memory addresses and the automatic incrementing of addresses does not stop at the highest used CRAM address. The user of this expert mode must be fully acquainted with the relevant procedures. More information concerning the functions of this device, such as the number of coefficients per function, their default values, memory addresses, etc., can be supplied on request at a later date. 11 I2S-BUS DESCRIPTION The feature interface of the TDA9870A contains two serial audio inputs and outputs and associated clock signals. It can be used to supply, for example, audio signals from received TV programs to a digital audio output device (AES/EBU format), or import serial audio signals from other sources for reproduction through the TV set's loudspeaker and/or headphone channels. Apart from such simple data input or output, it is also possible to run audio signals through an external DSP, which performs some additional functions, such as room simulation, Dolby Surround Pro Logic etc. and feed those signals back into the loudspeaker and/or headphone channels of the TDA9870A. Two serial audio formats are supported at the feature interface, i.e. the I2S-bus format and a very similar MSB-aligned format. The difference is illustrated in Fig.7. In both formats the left audio channel of a stereo sample pair is output first and is placed on the serial data line (SDI for input, SDO for output) when the word select line (WS)
TDA9870A
is LOW. Data is written at the trailing edge of SCK and read at the leading edge of SCK. The most significant bit is sent first. At power-up, the outputs of the feature interface are 3-stated to reduce EMC and allow for combinations with other ICs. If output is desired, it has to be activated by means of an I2C-bus command. When the output is enabled, the serial audio data can be taken from pins SDO1 and SDO2. Depending on the signal source, switch and matrix positions, the output can be either mono, stereo or dual language sound on either output. The word select output is clocked with the audio sample frequency at 32 kHz. The serial clock output (SCK) is clocked at a frequency of 2.048 MHz. This means, that there are 64 clock pulses per pair of stereo output samples, or 32 clock pulses per sample. Depending again on the signal source, the number of significant bits on the serial data outputs, SDO1 and SDO2, is between 14 and 18. Apart from just feeding a digital audio device, such as a DAC or an AES/EBU transmitter, the serial data outputs can be connected directly to the serial inputs (loop-back connection) or first to an external device, e.g. a feature DSP such as the SAA7710 and then back to the serial inputs. In all of these configurations, the SCK and WS clocks will be generated by the TDA9870A, which then is the I2S-bus master. The serial data inputs, SDI1 and SDI2, are active at all times, independent of the serial data outputs being on or off. When the serial data outputs are off (either after power-up or via the appropriate I2C-bus command) serial data and clocks WS and SCK from a separate digital audio source can be fed into the TDA9870A, be processed and output in accordance with internal selector positions, provided that the following criteria are met: * 32 kHz audio sample frequency * 32 clock bits per sample * External timing and data synchronized to TDA9870A. In such cases, the external source is the I2S-bus master and the TDA9870A is the I2S-bus slave. To support synchronization of external devices or as a master clock for them, a system clock output, SYSCLK, is available from the TDA9870A. At power-up it is off. It can be enabled and the output frequency set via an I2C-bus command. Available output frequencies are 8.192, 12.288, 16.384 and 24.576 MHz.
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
handbook, full pagewidth
SCK
WS
SD
LSB
MSB
LSB
MSB
MGK112
one sample
a. I2S-bus format.
handbook, full pagewidth
SCK
WS
SD
LSB
MSB
LSB
MSB
MGK113
one sample
b. MSB-aligned format.
Fig.7 Serial audio interface formats.
1998 Aug 10
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
12 EXTERNAL COMPONENTS
TDA9870A
handbook, full pagewidth
i.c. i.c. ADDR1 SCL SDA VSSA1 VDEC1 C1 4.7 F R1 10 k P1 C2 SIFSAT 47 pF C4 SIFTV 47 pF ADDR2 VSSD1 +5 V R2 1.5 C5 47 F C6 1 F VDDD1 CRESET VSSD4 XTALI 24.576 MHz C3 100 nF SIF1 SIF2 Vref1 Iref
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDDD2 C35 LOR LOL MOL C31 MOR VDDA AUXOL C26 AUXOR C24 VSSA3 PCAPL PCAPR Vref3 SCOL2 SCOR2 VSSA4 VSSD2 SCOL1 SCOR1 Vref2 i.c. i.c. VSSA2 i.c. i.c. Vref(n) Vref(p) C15 47 F R7 270 C16 47 F C17 C21 47 F C19 C23 10 nF C29 C28 10 nF
R19 47 F 1.5 C34
+5 V
C33
2.2 F
2.2 F C32 C30 2.2 F R8
10 nF 2.2 F 47 F C27
2.2 C25 2.2 F
+5 V
10 nF 2.2 F 10 nF
C22 10 nF C20 2.2 F
2.2 F
TDA9870A
17 18 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
MHB115
C18 2.2 F
2.2 F
XTALO 19 P2 SYSCLK SCK WS SDO2 SDO1 SDI2 SDI1 TEST1 20 21 22 23 24 25 26 27 28 29 30 31 32
VDEC2 SCIL2 SCIR2 VSSD3 SCIL1 SCIR1 R3 R6 15 k R5
C14 4.7 F
C13 330 nF C12 330 nF C11
C7 470 nF C8 470 nF C9 470 nF
MONOIN TEST2 EXTIR EXTIL
15 k
R4
15 k 330 nF C10 330 nF
15 k
Fig.8 Schematic for measurements.
1998 Aug 10
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
13 APPLICATION CIRCUITRY
handbook, full pagewidth POWER
C1 0V +5 V 47 F L9 C42 i.c. ADDR1 R1 100 R2 L1 L2 SCL SDA VSSA1 VDEC1 C2 470 nF R4 2.2 k C3 SIFSAT 47 pF C5 SIFTV 47 pF ADDR2 VSSD1 +5 V R5 1 L5 C6 470 nF C7 1 F VDDD1 CRESET VSSD4 XTALI 24.576 MHz R6 2.2 k 13 14 15 16 52 51 50 49 L4 C4 100 nF SIF1 12 53 L3 R3 10 k P1 SIF2 Vref1 9 10 11 56 55 54 Iref 2 3 4 5 6 7 8 63 62 61 60 59 58 57 LOR C40 LOL C38 MOL C36 MOR VDDA AUXOL C31 AUXOR C30 VSSA3 PCAPL PCAPR Vref3 SCOL2 SCOR2 VSSA4 VSSD2 SCOL1 C20 18 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
MHB116
TDA9870A
i.c.
1
64
VDDD2
R13 470 1 C41 nF C39 2.2 F
+5 V
470 pF
470 pF 2.2 F C37 10 nF C35 2.2 F
100
C34 C32
10 nF 2.2 F R12 470 nF C33 2.2
+5 V
10 nF 2.2 F C29 10 nF 2.2 F
C28 10 nF C26 47 F C24 C22 470 pF C27 10 nF C25 C23 2.2 F
470 pF 2.2 F
TDA9870A
17 48
C21 470 pF C19 2.2 F
SCOR1 C18 Vref2 i.c. i.c. VSSA2 i.c. i.c. Vref(n) Vref(p) C16 47 F R11 270 C14 R9
470 pF 2.2 F C17 47 F
XTALO 19 P2 SYSCLK SCK WS SDO2 SDO1 SDI2 SDI1 TEST1 20 21 22 23 24 25 26 27 28 29 30 31 32
VDEC2 SCIL2 R10 15 k SCIR2 VSSD3 SCIL1 SCIR1 R7
C15 470 nF
C8 470 nF C9
L6 MONOIN TEST2 L7 EXTIR L8 EXTIL
330 nF C13 330 nF C12
15 k
R8
470 nF C10 470 nF
15 k 330 nF C11 330 nF
15 k
note: L's are ferrite beads.
Fig.9 Schematic for application.
1998 Aug 10
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
14 PACKAGE OUTLINE SDIP64: plastic shrink dual in-line package; 64 leads (750 mil)
TDA9870A
SOT274-1
seating plane
D
ME
A2 A
L
A1 c Z e b1 b 64 33 wM (e 1) MH
pin 1 index E
1
32
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.84 A1 min. 0.51 A2 max. 4.57 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 58.67 57.70 E (1) 17.2 16.9 e 1.778 e1 19.05 L 3.2 2.8 ME 19.61 19.05 MH 20.96 19.71 w 0.18 Z (1) max. 1.73
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT274-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-10-13 95-02-04
1998 Aug 10
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Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
15 SOLDERING 15.1 Introduction
TDA9870A
time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 15.3 Repairing soldered joints
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 15.2 Soldering by dipping or by wave
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact 16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 Aug 10
84
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
NOTES
TDA9870A
1998 Aug 10
85
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
NOTES
TDA9870A
1998 Aug 10
86
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
NOTES
TDA9870A
1998 Aug 10
87
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 Internet: http://www.semiconductors.philips.com
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/1200/01/pp88
Date of release: 1998 Aug 10
Document order number:
9397 750 03839

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